EDN Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	22.012us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.770s	22.592us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.960s	123.391us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.290s	180.032us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.190s	36.281us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.880s	18.934us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	123.391us	1	1	100.00
		edn_csr_aliasing	1.190s	36.281us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.340s	41.578us	1	1	100.00
V2	csrng_commands	edn_genbits	1.340s	41.578us	1	1	100.00
V2	genbits	edn_genbits	1.340s	41.578us	1	1	100.00
V2	interrupts	edn_intr	1.110s	20.281us	1	1	100.00
V2	alerts	edn_alert	0.900s	73.087us	1	1	100.00
V2	errs	edn_err	0.960s	39.542us	1	1	100.00
V2	disable	edn_disable	0.870s	53.975us	1	1	100.00
		edn_disable_auto_req_mode	1.150s	47.894us	1	1	100.00
V2	stress_all	edn_stress_all	1.880s	166.949us	1	1	100.00
V2	intr_test	edn_intr_test	0.810s	13.727us	1	1	100.00
V2	alert_test	edn_alert_test	0.920s	92.344us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.000s	86.221us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.000s	86.221us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.770s	22.592us	1	1	100.00
		edn_csr_rw	0.960s	123.391us	1	1	100.00
		edn_csr_aliasing	1.190s	36.281us	1	1	100.00
		edn_same_csr_outstanding	1.070s	28.601us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.770s	22.592us	1	1	100.00
		edn_csr_rw	0.960s	123.391us	1	1	100.00
		edn_csr_aliasing	1.190s	36.281us	1	1	100.00
		edn_same_csr_outstanding	1.070s	28.601us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.600s	671.879us	1	1	100.00
		edn_tl_intg_err	1.930s	1.281ms	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.010s	23.203us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.900s	73.087us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.600s	671.879us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.600s	671.879us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.600s	671.879us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.600s	671.879us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.900s	73.087us	1	1	100.00
		edn_sec_cm	5.600s	671.879us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.900s	73.087us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.930s	1.281ms	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.343m	20.374ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00