HMAC Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.750s 1.018ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.760s 41.330us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.990s 27.435us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.960s 226.165us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.980s 187.845us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.520s 85.701us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.990s 27.435us 1 1 100.00
hmac_csr_aliasing 3.980s 187.845us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 26.190s 3.932ms 1 1 100.00
V2 back_pressure hmac_back_pressure 36.220s 1.427ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.106m 11.849ms 1 1 100.00
hmac_test_sha384_vectors 19.200s 714.948us 1 1 100.00
hmac_test_sha512_vectors 7.091m 71.511ms 1 1 100.00
hmac_test_hmac256_vectors 9.730s 1.239ms 1 1 100.00
hmac_test_hmac384_vectors 10.020s 696.841us 1 1 100.00
hmac_test_hmac512_vectors 8.690s 245.592us 1 1 100.00
V2 burst_wr hmac_burst_wr 21.230s 6.294ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.496m 1.250ms 1 1 100.00
V2 error hmac_error 50.040s 3.930ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 21.400s 10.940ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.750s 1.018ms 1 1 100.00
hmac_long_msg 26.190s 3.932ms 1 1 100.00
hmac_back_pressure 36.220s 1.427ms 1 1 100.00
hmac_datapath_stress 2.496m 1.250ms 1 1 100.00
hmac_burst_wr 21.230s 6.294ms 1 1 100.00
hmac_stress_all 3.432m 19.938ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.750s 1.018ms 1 1 100.00
hmac_long_msg 26.190s 3.932ms 1 1 100.00
hmac_back_pressure 36.220s 1.427ms 1 1 100.00
hmac_datapath_stress 2.496m 1.250ms 1 1 100.00
hmac_wipe_secret 21.400s 10.940ms 1 1 100.00
hmac_test_sha256_vectors 3.106m 11.849ms 1 1 100.00
hmac_test_sha384_vectors 19.200s 714.948us 1 1 100.00
hmac_test_sha512_vectors 7.091m 71.511ms 1 1 100.00
hmac_test_hmac256_vectors 9.730s 1.239ms 1 1 100.00
hmac_test_hmac384_vectors 10.020s 696.841us 1 1 100.00
hmac_test_hmac512_vectors 8.690s 245.592us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.750s 1.018ms 1 1 100.00
hmac_long_msg 26.190s 3.932ms 1 1 100.00
hmac_back_pressure 36.220s 1.427ms 1 1 100.00
hmac_datapath_stress 2.496m 1.250ms 1 1 100.00
hmac_burst_wr 21.230s 6.294ms 1 1 100.00
hmac_error 50.040s 3.930ms 1 1 100.00
hmac_wipe_secret 21.400s 10.940ms 1 1 100.00
hmac_test_sha256_vectors 3.106m 11.849ms 1 1 100.00
hmac_test_sha384_vectors 19.200s 714.948us 1 1 100.00
hmac_test_sha512_vectors 7.091m 71.511ms 1 1 100.00
hmac_test_hmac256_vectors 9.730s 1.239ms 1 1 100.00
hmac_test_hmac384_vectors 10.020s 696.841us 1 1 100.00
hmac_test_hmac512_vectors 8.690s 245.592us 1 1 100.00
hmac_stress_all 3.432m 19.938ms 1 1 100.00
V2 stress_all hmac_stress_all 3.432m 19.938ms 1 1 100.00
V2 alert_test hmac_alert_test 0.610s 16.519us 1 1 100.00
V2 intr_test hmac_intr_test 0.700s 40.661us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.650s 234.825us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.650s 234.825us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.760s 41.330us 1 1 100.00
hmac_csr_rw 0.990s 27.435us 1 1 100.00
hmac_csr_aliasing 3.980s 187.845us 1 1 100.00
hmac_same_csr_outstanding 1.760s 44.891us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.760s 41.330us 1 1 100.00
hmac_csr_rw 0.990s 27.435us 1 1 100.00
hmac_csr_aliasing 3.980s 187.845us 1 1 100.00
hmac_same_csr_outstanding 1.760s 44.891us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.180s 123.539us 1 1 100.00
hmac_tl_intg_err 1.640s 427.645us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.640s 427.645us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.750s 1.018ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.420s 28.887us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.410m 13.266ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.100s 232.884us 1 1 100.00
TOTAL 28 28 100.00