I2C Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	55.970s	7.019ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	23.910s	3.972ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.920s	200.945us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.930s	24.170us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.900s	1.080ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.470s	846.831us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.990s	30.186us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.930s	24.170us	1	1	100.00
		i2c_csr_aliasing	1.470s	846.831us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.910s	21.563us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.827m	5.976ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	43.440s	6.426ms	1	1	100.00
V2	host_override	i2c_host_override	0.940s	18.215us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.658m	3.886ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	38.730s	6.217ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.240s	241.801us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.180s	232.730us	1	1	100.00
		i2c_host_fifo_reset_rx	3.340s	409.569us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.372m	4.703ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	17.050s	561.073us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.930s	206.428us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.700s	863.214us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.657m	24.235ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.950s	709.330us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.850s	3.382ms	1	1	100.00
		i2c_target_intr_smoke	3.720s	822.155us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.090s	345.620us	1	1	100.00
		i2c_target_fifo_reset_tx	1.420s	463.640us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	55.960s	56.922ms	1	1	100.00
		i2c_target_stress_rd	12.850s	3.382ms	1	1	100.00
		i2c_target_intr_stress_wr	3.974m	23.482ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	8.230s	1.561ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.300s	332.830us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.430s	975.094us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.360s	889.154us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.220s	638.630us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.290s	154.692us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	43.440s	6.426ms	1	1	100.00
		i2c_host_perf_precise	18.090s	559.877us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	17.050s	561.073us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.100s	132.760us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.020s	641.032us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	2.303ms	1	1	100.00
		i2c_target_nack_txstretch	1.180s	561.874us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	16.040s	620.358us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.280s	1.075ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.760s	45.778us	1	1	100.00
V2	intr_test	i2c_intr_test	0.960s	17.505us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.420s	48.211us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.420s	48.211us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.920s	200.945us	1	1	100.00
		i2c_csr_rw	0.930s	24.170us	1	1	100.00
		i2c_csr_aliasing	1.470s	846.831us	1	1	100.00
		i2c_same_csr_outstanding	0.990s	59.258us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.920s	200.945us	1	1	100.00
		i2c_csr_rw	0.930s	24.170us	1	1	100.00
		i2c_csr_aliasing	1.470s	846.831us	1	1	100.00
		i2c_same_csr_outstanding	0.990s	59.258us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.670s	100.485us	1	1	100.00
		i2c_sec_cm	0.960s	97.409us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.670s	100.485us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	13.530s	12.161ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.680s	319.101us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.080s	1.588ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.70551167974903190084519931672878372986508786068976661057648979634560358355776
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  21563094 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  21563094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.29718672712624855568120887884044449358867048334347336882577932562512077133596
      Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 5976189794 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 5976189794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.22733996168053069321178990531731879696095133078855199846687816695242623680936
      Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1587584473 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1587584473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.8987923538350700669118443273253358971599800956141797111835971625542926896278
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 863213652 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 863213652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.71667126308666468702731885376053383648714496115629155121082699990971136669394
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 319101206 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 143 [0x8f])
        UVM_INFO @ 319101206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.5908179904108054817006735039167014661684333685040803957927319198790383926572
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12161114049 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12161114049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.36493518165182853088719804915895256739955826562214689532182084306196176187011
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 206428230 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x45a50894, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 206428230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---