KEYMGR Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.060s 78.532us 1 1 100.00
V1 random keymgr_random 2.490s 548.936us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.800s 233.936us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.900s 50.851us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 8.700s 521.656us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 4.810s 1.512ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.070s 224.925us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.900s 50.851us 1 1 100.00
keymgr_csr_aliasing 4.810s 1.512ms 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 7.290s 839.278us 1 1 100.00
V2 sideload keymgr_sideload 2.170s 55.751us 1 1 100.00
keymgr_sideload_kmac 3.480s 239.151us 1 1 100.00
keymgr_sideload_aes 20.820s 3.140ms 1 1 100.00
keymgr_sideload_otbn 2.360s 101.680us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.410s 86.954us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.220s 61.993us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.620s 170.739us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.790s 42.565us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.270s 222.350us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.340s 23.824us 1 1 100.00
V2 stress_all keymgr_stress_all 11.560s 1.892ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.690s 97.098us 1 1 100.00
V2 alert_test keymgr_alert_test 0.690s 52.186us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.570s 356.876us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.570s 356.876us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.800s 233.936us 1 1 100.00
keymgr_csr_rw 0.900s 50.851us 1 1 100.00
keymgr_csr_aliasing 4.810s 1.512ms 1 1 100.00
keymgr_same_csr_outstanding 1.280s 102.491us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.800s 233.936us 1 1 100.00
keymgr_csr_rw 0.900s 50.851us 1 1 100.00
keymgr_csr_aliasing 4.810s 1.512ms 1 1 100.00
keymgr_same_csr_outstanding 1.280s 102.491us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 9.240s 473.185us 1 1 100.00
keymgr_tl_intg_err 3.480s 227.358us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 4.180s 782.676us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 4.180s 782.676us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 4.180s 782.676us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 4.180s 782.676us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.970s 244.118us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.480s 227.358us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 4.180s 782.676us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 7.290s 839.278us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 2.490s 548.936us 1 1 100.00
keymgr_csr_rw 0.900s 50.851us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 2.490s 548.936us 1 1 100.00
keymgr_csr_rw 0.900s 50.851us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 2.490s 548.936us 1 1 100.00
keymgr_csr_rw 0.900s 50.851us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.220s 61.993us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.270s 222.350us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.270s 222.350us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 2.490s 548.936us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 2.550s 101.325us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.040s 206.747us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.220s 61.993us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.040s 206.747us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.040s 206.747us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.040s 206.747us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 9.240s 473.185us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.040s 206.747us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 4.630s 190.088us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00