| V1 |
smoke |
kmac_smoke |
2.950s |
131.968us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.200s |
30.143us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.270s |
50.829us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
8.190s |
2.915ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
5.790s |
134.968us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.240s |
167.451us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.270s |
50.829us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.790s |
134.968us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
1.070s |
43.117us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.330s |
67.291us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
32.582m |
224.754ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
13.238m |
26.615ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
31.503m |
768.088ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
23.597m |
23.203ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.979m |
13.351ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
16.856m |
42.998ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.019m |
27.152ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
28.745m |
117.763ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.610s |
223.196us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.240s |
280.661us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
1.630m |
3.902ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
35.420s |
3.881ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
2.561m |
8.943ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
2.542m |
9.790ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
4.016m |
191.692ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
7.140s |
6.587ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.990s |
754.894us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.070s |
73.795us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.620s |
26.903us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
56.710s |
8.070ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.420s |
103.948us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
3.318m |
11.083ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.980s |
17.197us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.930s |
64.750us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.990s |
3.159ms |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.990s |
3.159ms |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.200s |
30.143us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.270s |
50.829us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.790s |
134.968us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.670s |
263.512us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.200s |
30.143us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.270s |
50.829us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.790s |
134.968us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.670s |
263.512us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
2.260s |
147.364us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
2.260s |
147.364us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
2.260s |
147.364us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
2.260s |
147.364us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.610s |
99.061us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
40.450s |
4.805ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.100s |
131.331us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.100s |
131.331us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.420s |
103.948us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
2.950s |
131.968us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
1.630m |
3.902ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
2.260s |
147.364us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
40.450s |
4.805ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
40.450s |
4.805ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
40.450s |
4.805ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
2.950s |
131.968us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.420s |
103.948us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
40.450s |
4.805ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
2.643m |
7.316ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
2.950s |
131.968us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.339m |
18.662ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |