KMAC/UNMASKED Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	30.880s	2.024ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.930s	23.529us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.230s	18.225us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.980s	5.384ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.190s	390.787us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.890s	52.654us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	18.225us	1	1	100.00
		kmac_csr_aliasing	6.190s	390.787us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.980s	12.647us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.150s	67.614us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.571m	15.408ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.643m	38.960ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	20.642m	71.060ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.900s	1.647ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.212m	553.898ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.950s	285.479us	1	1	100.00
		kmac_test_vectors_shake_128	24.703m	20.541ms	1	1	100.00
		kmac_test_vectors_shake_256	25.791m	389.574ms	1	1	100.00
		kmac_test_vectors_kmac	2.280s	65.623us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.510s	60.739us	1	1	100.00
V2	sideload	kmac_sideload	3.572m	7.619ms	1	1	100.00
V2	app	kmac_app	47.340s	6.964ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.970s	1.389ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.289m	3.832ms	1	1	100.00
V2	error	kmac_error	3.289m	55.000ms	1	1	100.00
V2	key_error	kmac_key_error	2.070s	368.049us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.419m	10.021ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	20.260s	584.220us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	21.530s	1.726ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	29.510s	3.480ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.520s	105.706us	1	1	100.00
V2	stress_all	kmac_stress_all	4.981m	19.770ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.950s	17.167us	1	1	100.00
V2	alert_test	kmac_alert_test	1.080s	96.508us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.490s	477.632us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.490s	477.632us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.930s	23.529us	1	1	100.00
		kmac_csr_rw	1.230s	18.225us	1	1	100.00
		kmac_csr_aliasing	6.190s	390.787us	1	1	100.00
		kmac_same_csr_outstanding	2.460s	284.215us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.930s	23.529us	1	1	100.00
		kmac_csr_rw	1.230s	18.225us	1	1	100.00
		kmac_csr_aliasing	6.190s	390.787us	1	1	100.00
		kmac_same_csr_outstanding	2.460s	284.215us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.700s	39.130us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.700s	39.130us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.700s	39.130us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.700s	39.130us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.040s	250.595us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	55.170s	11.194ms	1	1	100.00
		kmac_tl_intg_err	2.440s	1.072ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.440s	1.072ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.520s	105.706us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	30.880s	2.024ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.572m	7.619ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.700s	39.130us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.170s	11.194ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.170s	11.194ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.170s	11.194ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	30.880s	2.024ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.520s	105.706us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.170s	11.194ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	35.750s	1.084ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	30.880s	2.024ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.130s	10.890ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.8238843058144816586024264812874111063586415322341868415578908097672318748113
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10021000168 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb1ad000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10021000168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---