ROM_CTRL/64KB Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.830s 298.240us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.510s 394.006us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.020s 536.972us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.710s 1.069ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.300s 216.880us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.190s 336.658us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.020s 536.972us 1 1 100.00
rom_ctrl_csr_aliasing 7.300s 216.880us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.540s 206.916us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.710s 298.070us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.740s 677.540us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 31.030s 4.241ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.240s 2.797ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 8.600s 3.110ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.360s 988.951us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.360s 988.951us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.510s 394.006us 1 1 100.00
rom_ctrl_csr_rw 7.020s 536.972us 1 1 100.00
rom_ctrl_csr_aliasing 7.300s 216.880us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.410s 699.527us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.510s 394.006us 1 1 100.00
rom_ctrl_csr_rw 7.020s 536.972us 1 1 100.00
rom_ctrl_csr_aliasing 7.300s 216.880us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.410s 699.527us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 40.770s 1.565ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.216m 686.627us 1 1 100.00
rom_ctrl_tl_intg_err 1.651m 366.088us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.216m 686.627us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.216m 686.627us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.216m 686.627us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.216m 686.627us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.830s 298.240us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.830s 298.240us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.830s 298.240us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.651m 366.088us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.240s 2.797ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.366m 12.743ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 40.770s 1.565ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.216m 686.627us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.760m 26.697ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00