RV_TIMER Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.960s	58.251us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.770s	48.065us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.550s	40.950us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.200s	203.098us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.850s	71.949us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.190s	29.346us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.550s	40.950us	1	1	100.00
		rv_timer_csr_aliasing	0.850s	71.949us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.590s	47.123us	1	1	100.00
V2	disabled	rv_timer_disabled	0.660s	101.473us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	15.140s	13.392ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	15.140s	13.392ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.970s	4.123ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.810s	43.784us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.750s	13.708us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.290s	241.619us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.290s	241.619us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.770s	48.065us	1	1	100.00
		rv_timer_csr_rw	0.550s	40.950us	1	1	100.00
		rv_timer_csr_aliasing	0.850s	71.949us	1	1	100.00
		rv_timer_same_csr_outstanding	0.810s	51.937us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.770s	48.065us	1	1	100.00
		rv_timer_csr_rw	0.550s	40.950us	1	1	100.00
		rv_timer_csr_aliasing	0.850s	71.949us	1	1	100.00
		rv_timer_same_csr_outstanding	0.810s	51.937us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	0.790s	60.675us	1	1	100.00
		rv_timer_tl_intg_err	1.000s	90.816us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.000s	90.816us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	6.430s	953.948us	0	1	0.00
V3	max_value	rv_timer_max	0.650s	180.658us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	4.260s	4.617ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.55057392024831507951580161443101779692782267415368968041141052795670529338551
      Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 953947952 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6ed94504) == 0x1
        UVM_INFO @ 953947952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.115020646850037513146864494659746953955258605697102760274171780701384995094938
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 180657754 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 180657754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.39583090815796343714737917141792315401242213486521435702098852594838102206228
      Line 141, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 4617105133 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 4617105133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---