SPI_DEVICE/1R1W Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	48.040s	6.753ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	41.431us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.800s	139.373us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.820s	440.802us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.360s	1.167ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.820s	1.112ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.800s	139.373us	1	1	100.00
		spi_device_csr_aliasing	14.360s	1.167ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	38.376us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.590s	79.326us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.950s	31.460us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.830s	5.913us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.670s	3.827us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.780s	121.116us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.780s	121.116us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.550s	1.035ms	1	1	100.00
		spi_device_tpm_sts_read	0.880s	35.306us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	30.640s	38.329ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	12.640s	16.214ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	20.220s	11.983ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	20.220s	11.983ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.840s	1.684ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.840s	1.684ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.840s	1.684ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.840s	1.684ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.840s	1.684ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	19.160s	8.427ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.460s	8.308ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.460s	8.308ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.460s	8.308ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.930s	444.767us	1	1	100.00
		spi_device_read_buffer_direct	11.780s	3.658ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.460s	8.308ms	1	1	100.00
		spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	34.440s	4.049ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.590s	3.475ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.590s	3.475ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	48.040s	6.753ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	0.980s	74.368us	1	1	100.00
V2	stress_all	spi_device_stress_all	1.197m	121.245ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.930s	19.064us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.950s	43.506us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.620s	326.363us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.620s	326.363us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	41.431us	1	1	100.00
		spi_device_csr_rw	1.800s	139.373us	1	1	100.00
		spi_device_csr_aliasing	14.360s	1.167ms	1	1	100.00
		spi_device_same_csr_outstanding	1.530s	282.916us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	41.431us	1	1	100.00
		spi_device_csr_rw	1.800s	139.373us	1	1	100.00
		spi_device_csr_aliasing	14.360s	1.167ms	1	1	100.00
		spi_device_same_csr_outstanding	1.530s	282.916us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.010s	40.031us	1	1	100.00
		spi_device_tl_intg_err	17.500s	3.245ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.500s	3.245ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.233m	35.929ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.59713265937438448590478927719375271483952342657711176429543113217328119390336
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3193002 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[24])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3193002 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3193002 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.52785787158176779359998044605765400848195099220734582714461845823708845677598
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1636312 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x375b2a [1101110101101100101010] vs 0x0 [0])
        UVM_ERROR @   1657312 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xef95c3 [111011111001010111000011] vs 0x0 [0])
        UVM_ERROR @   1709312 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa5d864 [101001011101100001100100] vs 0x0 [0])
        UVM_ERROR @   1789312 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8f0fbd [100011110000111110111101] vs 0x0 [0])
        UVM_ERROR @   1812312 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x73585 [1110011010110000101] vs 0x0 [0])