SPI_DEVICE/2P Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.537m	17.949ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.290s	39.460us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.060s	197.237us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.920s	913.146us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.640s	7.534ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.440s	50.932us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.060s	197.237us	1	1	100.00
		spi_device_csr_aliasing	14.640s	7.534ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.880s	11.606us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.280s	70.349us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.830s	124.032us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.940s	212.514us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.690s	36.825us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	0.940s	18.550us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.940s	18.550us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.180s	35.763ms	1	1	100.00
		spi_device_tpm_sts_read	0.730s	13.047us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.390s	8.983ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.990s	358.772us	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.820s	1.882ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.820s	1.882ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	11.370s	1.750ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	11.370s	1.750ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.370s	1.750ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	11.370s	1.750ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	11.370s	1.750ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.630s	56.662us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.910s	1.095ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.910s	1.095ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.910s	1.095ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.990s	1.473ms	1	1	100.00
		spi_device_read_buffer_direct	4.200s	352.587us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.910s	1.095ms	1	1	100.00
		spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	6.200s	2.553ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.930s	707.131us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.930s	707.131us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.537m	17.949ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.118m	49.717ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.167m	26.003ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.790s	50.000us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.790s	15.527us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.300s	48.801us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.300s	48.801us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.290s	39.460us	1	1	100.00
		spi_device_csr_rw	2.060s	197.237us	1	1	100.00
		spi_device_csr_aliasing	14.640s	7.534ms	1	1	100.00
		spi_device_same_csr_outstanding	3.030s	518.167us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.290s	39.460us	1	1	100.00
		spi_device_csr_rw	2.060s	197.237us	1	1	100.00
		spi_device_csr_aliasing	14.640s	7.534ms	1	1	100.00
		spi_device_same_csr_outstanding	3.030s	518.167us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.900s	84.013us	1	1	100.00
		spi_device_tl_intg_err	17.640s	4.449ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.640s	4.449ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	22.000s	6.026ms	1	1	100.00
		TOTAL			33	33	100.00