SRAM_CTRL/MAIN Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.380s	1.820ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.910s	16.022us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.800s	31.600us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.320s	106.813us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.080s	39.741us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.490s	504.205us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.800s	31.600us	1	1	100.00
		sram_ctrl_csr_aliasing	1.080s	39.741us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.696m	10.941ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.963m	12.754ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.411m	46.194ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.425m	4.323ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	9.255m	11.344ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	57.500s	8.919ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	27.990s	7.115ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.371m	109.205ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.670s	1.460ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.316m	91.735ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	55.710s	795.817us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.370s	753.977us	1	1	100.00
		sram_ctrl_throughput_w_readback	11.670s	785.504us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.530m	2.895ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.190s	6.726ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	23.298m	54.721ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.910s	47.894us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.280s	560.624us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.280s	560.624us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.910s	16.022us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	31.600us	1	1	100.00
		sram_ctrl_csr_aliasing	1.080s	39.741us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.020s	60.358us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.910s	16.022us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	31.600us	1	1	100.00
		sram_ctrl_csr_aliasing	1.080s	39.741us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.020s	60.358us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.190s	7.522ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.910s	4.682us	0	1	0.00
		sram_ctrl_tl_intg_err	2.850s	357.875us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.910s	4.682us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.850s	357.875us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.530m	2.895ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.530m	2.895ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.800s	31.600us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.371m	109.205ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.371m	109.205ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.371m	109.205ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	27.990s	7.115ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.310s	680.777us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.190s	7.522ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.750s	694.857us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.380s	1.820ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.380s	1.820ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.371m	109.205ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.910s	4.682us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	27.990s	7.115ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.910s	4.682us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.910s	4.682us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.380s	1.820ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.910s	4.682us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.440s	231.099us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.62539906405384831507596479199733999168926942812243768803941262326393442609660
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4682263 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4682263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---