SRAM_CTRL/RET Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	40.780s	2.246ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	13.015us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	12.669us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.580s	124.871us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	85.321us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.960s	75.270us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	12.669us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	85.321us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.160s	498.147us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.060s	252.406us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.634m	6.707ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.405m	5.783ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	13.910s	1.272ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.685m	3.234ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.100s	254.828us	1	1	100.00
V2	executable	sram_ctrl_executable	5.050m	5.204ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.880s	119.417us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.378m	12.065ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	38.080s	511.050us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	28.160s	261.549us	1	1	100.00
		sram_ctrl_throughput_w_readback	3.980s	311.714us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.300m	2.058ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.710s	26.769us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	18.598m	105.349ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.680s	30.236us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.800s	726.636us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.800s	726.636us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	13.015us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	12.669us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	85.321us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	28.744us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	13.015us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	12.669us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	85.321us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	28.744us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.560s	230.890us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.670s	6.279us	0	1	0.00
		sram_ctrl_tl_intg_err	1.830s	480.357us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.670s	6.279us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.830s	480.357us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.300m	2.058ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.300m	2.058ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	12.669us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.050m	5.204ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.050m	5.204ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.050m	5.204ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.100s	254.828us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.900s	122.867us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.560s	230.890us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.890s	34.851us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	40.780s	2.246ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	40.780s	2.246ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.050m	5.204ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.670s	6.279us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.100s	254.828us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.670s	6.279us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.670s	6.279us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	40.780s	2.246ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.670s	6.279us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.091m	3.854ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.1046852495904845263223088144924834919939211468467681871319943163360274497878
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 122866791 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 122866791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.56763916129248372706022422899066053344017520327158994491966096582625259381648
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6278745 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6278745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---