SYSRST_CTRL Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: `158897e`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.300s	2.111ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	3.070s	2.456ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.640s	2.188ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.120s	2.526ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.550s	6.047ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.750s	2.044ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	45.920s	26.398ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	6.140s	2.567ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.690s	2.048ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.750s	2.044ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.140s	2.567ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.958m	139.354ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	3.223m	94.250ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	7.332m	235.963ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.150s	3.573ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	3.190s	2.517ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	4.290s	2.210ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	9.110s	4.963ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.550s	2.641ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	1.690s	5.440ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	18.350s	36.529ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	13.090s	6.788ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	4.180s	2.011ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.610s	2.041ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	2.750s	2.356ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	2.750s	2.356ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.550s	6.047ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.750s	2.044ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.140s	2.567ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.330s	5.093ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.550s	6.047ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.750s	2.044ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.140s	2.567ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.330s	5.093ms	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	37.820s	42.073ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	10.350s	22.472ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	10.350s	22.472ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	3.000s	9.407ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

0.sysrst_ctrl_stress_all_with_rand_reset.64675638427719161554792296291764954569243352769285790357063360223418901459592
Line 412, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9406565299 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 9406719144 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 9406719144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---