UART Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.080s	1.018ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.780s	15.042us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.710s	12.945us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.060s	702.839us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.740s	23.390us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.040s	76.095us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.710s	12.945us	1	1	100.00
		uart_csr_aliasing	0.740s	23.390us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	29.790s	120.277ms	1	1	100.00
V2	parity	uart_smoke	1.080s	1.018ms	1	1	100.00
		uart_tx_rx	29.790s	120.277ms	1	1	100.00
V2	parity_error	uart_intr	6.132m	254.881ms	1	1	100.00
		uart_rx_parity_err	40.100s	81.372ms	1	1	100.00
V2	watermark	uart_tx_rx	29.790s	120.277ms	1	1	100.00
		uart_intr	6.132m	254.881ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.016m	321.988ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.661m	98.938ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	18.040s	29.366ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.132m	254.881ms	1	1	100.00
V2	rx_break_err	uart_intr	6.132m	254.881ms	1	1	100.00
V2	rx_timeout	uart_intr	6.132m	254.881ms	1	1	100.00
V2	perf	uart_perf	11.152m	20.264ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.210s	4.089ms	1	1	100.00
V2	line_loopback	uart_loopback	6.210s	4.089ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	0.750s	42.297us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.880s	5.486ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	15.940s	7.195ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	13.910s	4.302ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.954m	78.583ms	1	1	100.00
V2	stress_all	uart_stress_all	5.230s	12.472ms	1	1	100.00
V2	alert_test	uart_alert_test	0.600s	23.632us	1	1	100.00
V2	intr_test	uart_intr_test	0.680s	11.948us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.260s	209.825us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.260s	209.825us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.780s	15.042us	1	1	100.00
		uart_csr_rw	0.710s	12.945us	1	1	100.00
		uart_csr_aliasing	0.740s	23.390us	1	1	100.00
		uart_same_csr_outstanding	0.880s	188.073us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.780s	15.042us	1	1	100.00
		uart_csr_rw	0.710s	12.945us	1	1	100.00
		uart_csr_aliasing	0.740s	23.390us	1	1	100.00
		uart_same_csr_outstanding	0.880s	188.073us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.030s	235.245us	1	1	100.00
		uart_tl_intg_err	1.070s	116.896us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.070s	116.896us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.720s	4.572ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.23155091070122168374910032474492548086730519010735629344193712977301627995624
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @   4215737 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   4968294 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   5700233 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   6432172 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   7164111 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0