ADC_CTRL Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.370s	5.608ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.280s	848.737us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.550s	431.134us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	57.670s	26.743ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.060s	1.286ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.650s	430.108us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.550s	431.134us	1	1	100.00
		adc_ctrl_csr_aliasing	4.060s	1.286ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.290m	168.553ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.581m	165.463ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.075m	160.084ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	56.600s	322.892ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	32.370s	176.262ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.811m	603.643ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	41.420s	179.891ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.100m	325.488ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.280s	4.891ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	33.670s	28.309ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.074m	107.283ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.328m	186.680ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.850s	445.949us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.010s	296.158us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.380s	637.854us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.380s	637.854us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.280s	848.737us	1	1	100.00
		adc_ctrl_csr_rw	2.550s	431.134us	1	1	100.00
		adc_ctrl_csr_aliasing	4.060s	1.286ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.900s	4.193ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.280s	848.737us	1	1	100.00
		adc_ctrl_csr_rw	2.550s	431.134us	1	1	100.00
		adc_ctrl_csr_aliasing	4.060s	1.286ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.900s	4.193ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	6.890s	7.909ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.780s	4.484ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.780s	4.484ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.130s	18.147ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00