EDN Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.150s	27.463us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.030s	16.576us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.190s	27.184us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.010s	511.391us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.240s	36.984us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.870s	48.736us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.190s	27.184us	1	1	100.00
		edn_csr_aliasing	1.240s	36.984us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.480s	29.371us	1	1	100.00
V2	csrng_commands	edn_genbits	1.480s	29.371us	1	1	100.00
V2	genbits	edn_genbits	1.480s	29.371us	1	1	100.00
V2	interrupts	edn_intr	1.000s	21.086us	1	1	100.00
V2	alerts	edn_alert	1.450s	33.866us	1	1	100.00
V2	errs	edn_err	0.870s	28.658us	1	1	100.00
V2	disable	edn_disable	0.900s	47.709us	1	1	100.00
		edn_disable_auto_req_mode	1.140s	500.000us	0	1	0.00
V2	stress_all	edn_stress_all	4.850s	336.604us	1	1	100.00
V2	intr_test	edn_intr_test	1.080s	23.898us	1	1	100.00
V2	alert_test	edn_alert_test	0.980s	47.790us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.810s	84.158us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.810s	84.158us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.030s	16.576us	1	1	100.00
		edn_csr_rw	1.190s	27.184us	1	1	100.00
		edn_csr_aliasing	1.240s	36.984us	1	1	100.00
		edn_same_csr_outstanding	1.290s	22.929us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.030s	16.576us	1	1	100.00
		edn_csr_rw	1.190s	27.184us	1	1	100.00
		edn_csr_aliasing	1.240s	36.984us	1	1	100.00
		edn_same_csr_outstanding	1.290s	22.929us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	tl_intg_err	edn_sec_cm	4.640s	345.511us	1	1	100.00
		edn_tl_intg_err	2.270s	391.879us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.870s	27.862us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.450s	33.866us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.640s	345.511us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.640s	345.511us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.640s	345.511us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.640s	345.511us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.450s	33.866us	1	1	100.00
		edn_sec_cm	4.640s	345.511us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.450s	33.866us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.270s	391.879us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.940m	31.357ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			20	21	95.24

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable_auto_req_mode has 1 failures.

    • 0.edn_disable_auto_req_mode.5301106325542789155458113323133230837841999988209328091127904412586471637775
      Line 87, in log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---