HMAC Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.860s 225.797us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.690s 26.913us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.840s 463.098us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.950s 1.109ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.020s 685.050us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.440s 116.655us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.840s 463.098us 1 1 100.00
hmac_csr_aliasing 6.020s 685.050us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 19.640s 6.330ms 1 1 100.00
V2 back_pressure hmac_back_pressure 42.880s 4.179ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.208m 6.764ms 1 1 100.00
hmac_test_sha384_vectors 6.129m 21.638ms 1 1 100.00
hmac_test_sha512_vectors 18.440s 587.420us 1 1 100.00
hmac_test_hmac256_vectors 5.300s 634.687us 1 1 100.00
hmac_test_hmac384_vectors 6.480s 237.083us 1 1 100.00
hmac_test_hmac512_vectors 10.810s 2.195ms 1 1 100.00
V2 burst_wr hmac_burst_wr 6.240s 1.043ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.934m 6.913ms 1 1 100.00
V2 error hmac_error 13.480s 1.853ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 30.630s 2.867ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.860s 225.797us 1 1 100.00
hmac_long_msg 19.640s 6.330ms 1 1 100.00
hmac_back_pressure 42.880s 4.179ms 1 1 100.00
hmac_datapath_stress 5.934m 6.913ms 1 1 100.00
hmac_burst_wr 6.240s 1.043ms 1 1 100.00
hmac_stress_all 4.649m 21.397ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.860s 225.797us 1 1 100.00
hmac_long_msg 19.640s 6.330ms 1 1 100.00
hmac_back_pressure 42.880s 4.179ms 1 1 100.00
hmac_datapath_stress 5.934m 6.913ms 1 1 100.00
hmac_wipe_secret 30.630s 2.867ms 1 1 100.00
hmac_test_sha256_vectors 3.208m 6.764ms 1 1 100.00
hmac_test_sha384_vectors 6.129m 21.638ms 1 1 100.00
hmac_test_sha512_vectors 18.440s 587.420us 1 1 100.00
hmac_test_hmac256_vectors 5.300s 634.687us 1 1 100.00
hmac_test_hmac384_vectors 6.480s 237.083us 1 1 100.00
hmac_test_hmac512_vectors 10.810s 2.195ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.860s 225.797us 1 1 100.00
hmac_long_msg 19.640s 6.330ms 1 1 100.00
hmac_back_pressure 42.880s 4.179ms 1 1 100.00
hmac_datapath_stress 5.934m 6.913ms 1 1 100.00
hmac_burst_wr 6.240s 1.043ms 1 1 100.00
hmac_error 13.480s 1.853ms 1 1 100.00
hmac_wipe_secret 30.630s 2.867ms 1 1 100.00
hmac_test_sha256_vectors 3.208m 6.764ms 1 1 100.00
hmac_test_sha384_vectors 6.129m 21.638ms 1 1 100.00
hmac_test_sha512_vectors 18.440s 587.420us 1 1 100.00
hmac_test_hmac256_vectors 5.300s 634.687us 1 1 100.00
hmac_test_hmac384_vectors 6.480s 237.083us 1 1 100.00
hmac_test_hmac512_vectors 10.810s 2.195ms 1 1 100.00
hmac_stress_all 4.649m 21.397ms 1 1 100.00
V2 stress_all hmac_stress_all 4.649m 21.397ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 12.164us 1 1 100.00
V2 intr_test hmac_intr_test 0.570s 45.906us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.690s 196.704us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.690s 196.704us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.690s 26.913us 1 1 100.00
hmac_csr_rw 0.840s 463.098us 1 1 100.00
hmac_csr_aliasing 6.020s 685.050us 1 1 100.00
hmac_same_csr_outstanding 1.330s 522.929us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.690s 26.913us 1 1 100.00
hmac_csr_rw 0.840s 463.098us 1 1 100.00
hmac_csr_aliasing 6.020s 685.050us 1 1 100.00
hmac_same_csr_outstanding 1.330s 522.929us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.870s 588.954us 1 1 100.00
hmac_tl_intg_err 3.190s 333.278us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.190s 333.278us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.860s 225.797us 1 1 100.00
V3 stress_reset hmac_stress_reset 0.890s 71.706us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 11.920s 3.725ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.930s 12.669us 1 1 100.00
TOTAL 28 28 100.00