I2C Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	11.800s	2.774ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.500s	3.578ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.700s	33.465us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.720s	37.244us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.860s	250.763us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.410s	42.522us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.900s	193.177us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.720s	37.244us	1	1	100.00
		i2c_csr_aliasing	1.410s	42.522us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.990s	212.130us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	0.660s	263.674us	0	1	0.00
V2	host_maxperf	i2c_host_perf	9.460s	5.680ms	1	1	100.00
V2	host_override	i2c_host_override	0.620s	132.054us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.310m	9.058ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.542m	2.199ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.860s	936.119us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.560s	410.041us	1	1	100.00
		i2c_host_fifo_reset_rx	5.690s	175.977us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	40.640s	5.347ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.320s	658.975us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.630s	25.265us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.730s	430.117us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	29.820s	46.889ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.070s	1.670ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	32.430s	2.187ms	1	1	100.00
		i2c_target_intr_smoke	3.070s	888.740us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.130s	320.922us	1	1	100.00
		i2c_target_fifo_reset_tx	0.800s	134.122us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	13.294m	61.571ms	1	1	100.00
		i2c_target_stress_rd	32.430s	2.187ms	1	1	100.00
		i2c_target_intr_stress_wr	37.300s	25.123ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.200s	5.278ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	58.940s	5.115ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.340s	9.722ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.710s	1.039ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.260s	1.582ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.020s	336.095us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	9.460s	5.680ms	1	1	100.00
		i2c_host_perf_precise	1.540s	43.061us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.320s	658.975us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.440s	91.457us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.030s	2.209ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.570s	930.219us	1	1	100.00
		i2c_target_nack_txstretch	0.970s	1.369ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.820s	2.110ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.630s	865.630us	1	1	100.00
V2	alert_test	i2c_alert_test	0.710s	18.838us	1	1	100.00
V2	intr_test	i2c_intr_test	0.630s	34.565us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.090s	47.081us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.090s	47.081us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.700s	33.465us	1	1	100.00
		i2c_csr_rw	0.720s	37.244us	1	1	100.00
		i2c_csr_aliasing	1.410s	42.522us	1	1	100.00
		i2c_same_csr_outstanding	0.810s	68.032us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.700s	33.465us	1	1	100.00
		i2c_csr_rw	0.720s	37.244us	1	1	100.00
		i2c_csr_aliasing	1.410s	42.522us	1	1	100.00
		i2c_same_csr_outstanding	0.810s	68.032us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.660s	126.574us	1	1	100.00
		i2c_sec_cm	0.890s	74.581us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.660s	126.574us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.230s	3.538ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.040s	274.088us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.060s	938.010us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.90186402691920833327946351003572190678747932364131761342591350267632377861532
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 212130415 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 212130415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.87779814598886355886717820277656917333872537865260074132697596312241078461972
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 263673789 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 263673789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.27732972465264421168323613055361091619819527586714501687191705227791505402893
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  25265328 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  25265328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.9926821450260644169550104328841226664346523681173248298389179133659971508579
      Line 102, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3537786711 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3537786711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.95373316919216758128331389976290567542600783208517804093450913396265961863746
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 938009775 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 938009775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.105069648957917197362933976368593173509056995333227449501963581311491172747571
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 430117204 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 430117204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.2510508438697945000692532530630802180469623145804831696830438650978179373236
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 274088028 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 88 [0x58])
        UVM_INFO @ 274088028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---