KMAC/UNMASKED Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	7.980s	216.753us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.950s	36.260us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.870s	36.262us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.830s	759.651us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.100s	286.923us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.270s	44.149us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.870s	36.262us	1	1	100.00
		kmac_csr_aliasing	3.100s	286.923us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.670s	20.648us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.980s	20.183us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	18.743m	71.750ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.507m	12.671ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.046m	262.254ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.494m	186.022ms	1	1	100.00
		kmac_test_vectors_sha3_384	12.912m	89.324ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.174m	9.538ms	1	1	100.00
		kmac_test_vectors_shake_128	35.654m	421.254ms	1	1	100.00
		kmac_test_vectors_shake_256	1.616m	27.655ms	1	1	100.00
		kmac_test_vectors_kmac	2.160s	42.886us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.500s	55.156us	1	1	100.00
V2	sideload	kmac_sideload	1.603m	3.463ms	1	1	100.00
V2	app	kmac_app	3.255m	23.184ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.946m	9.058ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.053m	79.202ms	1	1	100.00
V2	error	kmac_error	33.770s	8.102ms	1	1	100.00
V2	key_error	kmac_key_error	3.600s	3.199ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.531m	10.111ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	22.250s	481.319us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	12.740s	635.075us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	28.060s	3.949ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.470s	44.667us	1	1	100.00
V2	stress_all	kmac_stress_all	58.890s	4.062ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.820s	28.161us	1	1	100.00
V2	alert_test	kmac_alert_test	1.220s	113.514us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.640s	271.202us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.640s	271.202us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.950s	36.260us	1	1	100.00
		kmac_csr_rw	0.870s	36.262us	1	1	100.00
		kmac_csr_aliasing	3.100s	286.923us	1	1	100.00
		kmac_same_csr_outstanding	1.670s	174.926us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.950s	36.260us	1	1	100.00
		kmac_csr_rw	0.870s	36.262us	1	1	100.00
		kmac_csr_aliasing	3.100s	286.923us	1	1	100.00
		kmac_same_csr_outstanding	1.670s	174.926us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.270s	265.948us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.270s	265.948us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.270s	265.948us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.270s	265.948us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.250s	1.016ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	44.410s	19.192ms	1	1	100.00
		kmac_tl_intg_err	2.220s	120.776us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.220s	120.776us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.470s	44.667us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	7.980s	216.753us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.603m	3.463ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.270s	265.948us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	44.410s	19.192ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	44.410s	19.192ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	44.410s	19.192ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	7.980s	216.753us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.470s	44.667us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	44.410s	19.192ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.591m	2.807ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	7.980s	216.753us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.056m	11.607ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.67835153554187609852101626614332292249348396804879142729121704223633721968208
      Line 88, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10110699877 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2fe56000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
        UVM_INFO @ 10110699877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---