OTBN Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 38.733us 0 1 0.00
V1 single_binary otbn_single 7.000s 23.493us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 33.331us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 25.344us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 85.081us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 12.809us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 5.000s 160.743us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 25.344us 1 1 100.00
otbn_csr_aliasing 4.000s 12.809us 1 1 100.00
V1 mem_walk otbn_mem_walk 19.000s 1.857ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 9.000s 734.074us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 23.000s 517.876us 0 1 0.00
V2 multi_error otbn_multi_err 54.000s 271.449us 0 1 0.00
V2 back_to_back otbn_multi 36.000s 471.301us 0 1 0.00
V2 stress_all otbn_stress_all 5.000s 50.544us 0 1 0.00
V2 lc_escalation otbn_escalate 4.000s 31.158us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 6.000s 113.748us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 7.000s 55.461us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 23.683us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 40.155us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 673.725us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 673.725us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 33.331us 1 1 100.00
otbn_csr_rw 4.000s 25.344us 1 1 100.00
otbn_csr_aliasing 4.000s 12.809us 1 1 100.00
otbn_same_csr_outstanding 5.000s 144.396us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 33.331us 1 1 100.00
otbn_csr_rw 4.000s 25.344us 1 1 100.00
otbn_csr_aliasing 4.000s 12.809us 1 1 100.00
otbn_same_csr_outstanding 5.000s 144.396us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 9.000s 44.105us 0 1 0.00
otbn_dmem_err 7.000s 20.223us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 6.000s 70.747us 0 1 0.00
otbn_controller_ispr_rdata_err 7.000s 79.987us 0 1 0.00
otbn_mac_bignum_acc_err 7.000s 72.803us 0 1 0.00
otbn_urnd_err 4.000s 47.647us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 15.626us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 23.293us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 4.000s 3.608us 0 1 0.00
V2S tl_intg_err otbn_sec_cm 6.183m 2.287ms 1 1 100.00
otbn_tl_intg_err 14.000s 517.796us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 19.000s 230.264us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 38.733us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 7.000s 20.223us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 9.000s 44.105us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 14.000s 517.796us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 4.000s 31.158us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 9.000s 44.105us 0 1 0.00
otbn_dmem_err 7.000s 20.223us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 113.748us 0 1 0.00
otbn_illegal_mem_acc 5.000s 15.626us 1 1 100.00
otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 9.000s 44.105us 0 1 0.00
otbn_dmem_err 7.000s 20.223us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 113.748us 0 1 0.00
otbn_illegal_mem_acc 5.000s 15.626us 1 1 100.00
otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 4.000s 31.158us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 9.000s 44.105us 0 1 0.00
otbn_dmem_err 7.000s 20.223us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 113.748us 0 1 0.00
otbn_illegal_mem_acc 5.000s 15.626us 1 1 100.00
otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 38.211us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 36.138us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 13.000s 226.392us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 13.000s 226.392us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 19.098us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 8.000s 82.982us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 304.636us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 304.636us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 10.000s 67.819us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 36.000s 471.301us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 9.000s 65.355us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 7.000s 23.493us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 6.183m 2.287ms 1 1 100.00
V2S TOTAL 6 20 30.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 32.000s 125.258us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 41 43.90

Failure Buckets