PATTGEN Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	50.660us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	12.977us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	26.487us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	792.013us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	29.858us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	218.077us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	26.487us	1	1	100.00
		pattgen_csr_aliasing	2.000s	29.858us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	10.000s	2.759ms	1	1	100.00
V2	error	pattgen_error	8.000s	106.616us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.569h	8.398s	1	1	100.00
V2	alert_test	pattgen_alert_test	1.000s	10.658us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	14.494us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	656.804us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	656.804us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	12.977us	1	1	100.00
		pattgen_csr_rw	1.000s	26.487us	1	1	100.00
		pattgen_csr_aliasing	2.000s	29.858us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	83.661us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	12.977us	1	1	100.00
		pattgen_csr_rw	1.000s	26.487us	1	1	100.00
		pattgen_csr_aliasing	2.000s	29.858us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	83.661us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	402.905us	1	1	100.00
		pattgen_sec_cm	2.000s	64.262us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	402.905us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.000s	3.986ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	43.884us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.92356579489160909309610303092089336781710121807819989741241202719532662670123
      Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.60418616618634391132387863855656783559472735457944734336707143126509737451741
      Line 118, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 568286739 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 568295333 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 568295333 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 568367496 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]