RV_TIMER Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.720s	351.261us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.540s	37.873us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.560s	25.191us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.460s	578.609us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.610s	120.748us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.880s	20.483us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.560s	25.191us	1	1	100.00
		rv_timer_csr_aliasing	0.610s	120.748us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.700s	147.002us	0	1	0.00
V2	disabled	rv_timer_disabled	1.020s	1.064ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.828m	651.220ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.828m	651.220ms	1	1	100.00
V2	stress	rv_timer_stress_all	6.290s	11.326ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.550s	43.513us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.540s	33.534us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.880s	161.794us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.880s	161.794us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.540s	37.873us	1	1	100.00
		rv_timer_csr_rw	0.560s	25.191us	1	1	100.00
		rv_timer_csr_aliasing	0.610s	120.748us	1	1	100.00
		rv_timer_same_csr_outstanding	0.660s	66.560us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.540s	37.873us	1	1	100.00
		rv_timer_csr_rw	0.560s	25.191us	1	1	100.00
		rv_timer_csr_aliasing	0.610s	120.748us	1	1	100.00
		rv_timer_same_csr_outstanding	0.660s	66.560us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.770s	404.204us	1	1	100.00
		rv_timer_tl_intg_err	0.740s	179.011us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.740s	179.011us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.550s	129.841us	1	1	100.00
V3	max_value	rv_timer_max	0.770s	42.960us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	0.790s	30.697us	0	1	0.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.68848547787230765038195867885141939384144129489784164474902058601029901420542
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  42959583 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  42959583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.18845707109054162652726042615776542413691681132965823957603865647780813916782
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 147002325 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x54213f04) == 0x1
        UVM_INFO @ 147002325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.62158384972523712658554881949759844293999649083138195214504629191238174757148
      Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  30697252 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @  30697252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---