SPI_DEVICE/1R1W Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	58.170s	7.070ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.160s	261.428us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.430s	37.145us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.690s	1.904ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	4.940s	113.387us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.000s	442.348us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.430s	37.145us	1	1	100.00
		spi_device_csr_aliasing	4.940s	113.387us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	40.707us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.540s	55.522us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.740s	13.608us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.670s	1.720us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	8.025us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.160s	45.963us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.160s	45.963us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.370s	8.031ms	1	1	100.00
		spi_device_tpm_sts_read	0.840s	73.138us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.230s	2.421ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.530s	2.877ms	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.880s	377.501us	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.880s	377.501us	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.800s	345.217us	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.800s	345.217us	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.800s	345.217us	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.800s	345.217us	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.800s	345.217us	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.320s	597.519us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.900s	3.358ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.900s	3.358ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.900s	3.358ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.820s	331.988us	1	1	100.00
		spi_device_read_buffer_direct	5.280s	8.935ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.900s	3.358ms	1	1	100.00
		spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	44.120s	19.880ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.890s	154.281us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.890s	154.281us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	58.170s	7.070ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	57.910s	28.142ms	1	1	100.00
V2	stress_all	spi_device_stress_all	14.160s	7.268ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.870s	44.286us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.010s	34.524us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.710s	212.795us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.710s	212.795us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.160s	261.428us	1	1	100.00
		spi_device_csr_rw	1.430s	37.145us	1	1	100.00
		spi_device_csr_aliasing	4.940s	113.387us	1	1	100.00
		spi_device_same_csr_outstanding	1.590s	336.586us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.160s	261.428us	1	1	100.00
		spi_device_csr_rw	1.430s	37.145us	1	1	100.00
		spi_device_csr_aliasing	4.940s	113.387us	1	1	100.00
		spi_device_same_csr_outstanding	1.590s	336.586us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.230s	107.484us	1	1	100.00
		spi_device_tl_intg_err	6.400s	866.113us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.400s	866.113us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	35.480s	29.845ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.86342942459044940749153696634319606116857708039202668251845628629464282692481
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1344958 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[67])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1344958 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1344958 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[963])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.58008497116132261122413227469311406815621476306466618336395685545396415972605
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   5759147 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x454078 [10001010100000001111000] vs 0x0 [0])
        UVM_ERROR @   5795147 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x40c31 [1000000110000110001] vs 0x0 [0])
        UVM_ERROR @   5891147 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf7a9ae [111101111010100110101110] vs 0x0 [0])
        UVM_ERROR @   5959147 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47dd1a [10001111101110100011010] vs 0x0 [0])
        UVM_ERROR @   5976147 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x53f678 [10100111111011001111000] vs 0x0 [0])