SPI_DEVICE/2P Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 46.780s 2.920ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.440s 95.371us 1 1 100.00
V1 csr_rw spi_device_csr_rw 1.200s 90.040us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 8.960s 425.509us 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 5.730s 111.178us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 1.410s 49.751us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.200s 90.040us 1 1 100.00
spi_device_csr_aliasing 5.730s 111.178us 1 1 100.00
V1 mem_walk spi_device_mem_walk 0.670s 50.787us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.760s 26.248us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 0.910s 51.184us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.040s 282.337us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.030s 18.526us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.540s 55.390us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.540s 55.390us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 1.190s 139.873us 1 1 100.00
spi_device_tpm_sts_read 1.070s 29.578us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 11.110s 9.557ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 10.270s 8.700ms 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 3.180s 555.606us 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 3.180s 555.606us 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 2.950s 138.570us 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 2.950s 138.570us 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 2.950s 138.570us 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 2.950s 138.570us 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 2.950s 138.570us 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 1.710s 40.110us 1 1 100.00
V2 mailbox_command spi_device_mailbox 11.290s 1.211ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 11.290s 1.211ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 11.290s 1.211ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 14.660s 1.912ms 1 1 100.00
spi_device_read_buffer_direct 2.540s 274.086us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 11.290s 1.211ms 1 1 100.00
spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.284m 13.667ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 4.030s 1.378ms 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 4.030s 1.378ms 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 46.780s 2.920ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 1.297m 14.195ms 1 1 100.00
V2 stress_all spi_device_stress_all 28.490s 4.978ms 1 1 100.00
V2 alert_test spi_device_alert_test 0.770s 50.736us 1 1 100.00
V2 intr_test spi_device_intr_test 0.880s 15.320us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.570s 349.444us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.570s 349.444us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.440s 95.371us 1 1 100.00
spi_device_csr_rw 1.200s 90.040us 1 1 100.00
spi_device_csr_aliasing 5.730s 111.178us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 61.703us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.440s 95.371us 1 1 100.00
spi_device_csr_rw 1.200s 90.040us 1 1 100.00
spi_device_csr_aliasing 5.730s 111.178us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 61.703us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.320s 108.257us 1 1 100.00
spi_device_tl_intg_err 15.360s 4.193ms 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 15.360s 4.193ms 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 1.826m 26.195ms 1 1 100.00
TOTAL 33 33 100.00