SPI_HOST Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	7.000s	463.723us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	19.684us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	15.941us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	962.464us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	47.728us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	83.610us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	15.941us	1	1	100.00
		spi_host_csr_aliasing	3.000s	47.728us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	40.646us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	7.000s	15.840us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	62.540us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	52.825us	1	1	100.00
		spi_host_error_cmd	1.000s	17.444us	1	1	100.00
		spi_host_event	15.000s	9.056ms	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	60.151us	1	1	100.00
V2	speed	spi_host_speed	3.000s	60.151us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	60.151us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	369.159us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	20.574us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	60.151us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	60.151us	1	1	100.00
V2	duplex	spi_host_smoke	7.000s	463.723us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	7.000s	463.723us	1	1	100.00
V2	stress_all	spi_host_stress_all	4.000s	450.962us	1	1	100.00
V2	spien	spi_host_spien	4.000s	263.713us	1	1	100.00
V2	stall	spi_host_status_stall	4.000s	264.170us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	233.848us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	52.825us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	52.545us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	53.748us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	35.244us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	35.244us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	19.684us	1	1	100.00
		spi_host_csr_rw	2.000s	15.941us	1	1	100.00
		spi_host_csr_aliasing	3.000s	47.728us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	157.925us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	19.684us	1	1	100.00
		spi_host_csr_rw	2.000s	15.941us	1	1	100.00
		spi_host_csr_aliasing	3.000s	47.728us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	157.925us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	181.616us	1	1	100.00
		spi_host_sec_cm	1.000s	74.670us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	181.616us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	21.000s	1.093ms	1	1	100.00
		TOTAL			26	26	100.00