SRAM_CTRL/MAIN Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.510s	481.970us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	21.669us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	41.368us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	0.990s	45.671us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	20.559us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.400s	378.225us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	41.368us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	20.559us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.598m	8.218ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.809m	2.555ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.176m	9.816ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.328m	5.862ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.407m	53.201ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.325m	25.486ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	46.280s	49.289ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.838m	24.488ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.210s	1.814ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.743m	17.609ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	26.620s	1.077ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.080s	703.452us	1	1	100.00
		sram_ctrl_throughput_w_readback	19.630s	817.817us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.646m	8.910ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.540s	1.975ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	16.774m	18.991ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.680s	20.275us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.680s	49.596us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.680s	49.596us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	21.669us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	41.368us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	20.559us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	300.630us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	21.669us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	41.368us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	20.559us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	300.630us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.740s	33.527ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.730s	8.861us	0	1	0.00
		sram_ctrl_tl_intg_err	2.020s	353.890us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.730s	8.861us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.020s	353.890us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.646m	8.910ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.646m	8.910ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	41.368us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.838m	24.488ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.838m	24.488ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.838m	24.488ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	46.280s	49.289ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.620s	3.498ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.740s	33.527ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.130s	2.748ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.510s	481.970us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.510s	481.970us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.838m	24.488ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.730s	8.861us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	46.280s	49.289ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.730s	8.861us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.730s	8.861us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.510s	481.970us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.730s	8.861us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.700s	1.051ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.103837250818072141209434098144199901487824208289413905370871325276972512037917
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8860745 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8860745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---