SYSRST_CTRL Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.650s 2.129ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.800s 2.466ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 1.430s 2.223ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.730s 2.263ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 8.890s 4.035ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 4.290s 2.034ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 28.700s 43.692ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 7.110s 2.742ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 1.620s 2.115ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 4.290s 2.034ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.110s 2.742ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 11.850s 55.162ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 47.220s 26.329ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 6.850s 3.739ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 5.160s 3.116ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.060s 2.509ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 1.760s 2.210ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.860s 3.623ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 4.840s 2.616ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.070s 8.686ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 35.940s 38.816ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 13.750s 17.537ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 1.000s 2.073ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.940s 2.030ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.330s 2.246ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.330s 2.246ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 8.890s 4.035ms 1 1 100.00
sysrst_ctrl_csr_rw 4.290s 2.034ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.110s 2.742ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.540s 7.713ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 8.890s 4.035ms 1 1 100.00
sysrst_ctrl_csr_rw 4.290s 2.034ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.110s 2.742ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.540s 7.713ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 17.580s 42.138ms 1 1 100.00
sysrst_ctrl_tl_intg_err 38.150s 22.201ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 38.150s 22.201ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 8.390s 4.504ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00