UART Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: e431c33

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.110s	468.704us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.450s	1.033ms	1	1	100.00
V1	csr_rw	uart_csr_rw	0.610s	60.013us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.000s	1.271ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.610s	88.166us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.630s	59.300us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.610s	60.013us	1	1	100.00
		uart_csr_aliasing	0.610s	88.166us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	41.730s	118.960ms	1	1	100.00
V2	parity	uart_smoke	1.110s	468.704us	1	1	100.00
		uart_tx_rx	41.730s	118.960ms	1	1	100.00
V2	parity_error	uart_intr	13.080s	40.646ms	1	1	100.00
		uart_rx_parity_err	45.040s	217.478ms	1	1	100.00
V2	watermark	uart_tx_rx	41.730s	118.960ms	1	1	100.00
		uart_intr	13.080s	40.646ms	1	1	100.00
V2	fifo_full	uart_fifo_full	35.110s	158.166ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	10.360s	36.519ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	19.930s	56.249ms	1	1	100.00
V2	rx_frame_err	uart_intr	13.080s	40.646ms	1	1	100.00
V2	rx_break_err	uart_intr	13.080s	40.646ms	1	1	100.00
V2	rx_timeout	uart_intr	13.080s	40.646ms	1	1	100.00
V2	perf	uart_perf	3.199m	5.881ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.530s	9.288ms	1	1	100.00
V2	line_loopback	uart_loopback	10.530s	9.288ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	47.080s	19.952ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.070s	5.218ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	18.540s	7.163ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.820s	2.634ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.726m	69.288ms	1	1	100.00
V2	stress_all	uart_stress_all	3.649m	32.714ms	1	1	100.00
V2	alert_test	uart_alert_test	0.540s	15.330us	1	1	100.00
V2	intr_test	uart_intr_test	0.560s	40.841us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.490s	112.407us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.490s	112.407us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.450s	1.033ms	1	1	100.00
		uart_csr_rw	0.610s	60.013us	1	1	100.00
		uart_csr_aliasing	0.610s	88.166us	1	1	100.00
		uart_same_csr_outstanding	0.660s	105.376us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.450s	1.033ms	1	1	100.00
		uart_csr_rw	0.610s	60.013us	1	1	100.00
		uart_csr_aliasing	0.610s	88.166us	1	1	100.00
		uart_same_csr_outstanding	0.660s	105.376us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.720s	42.876us	1	1	100.00
		uart_tl_intg_err	0.900s	50.782us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.900s	50.782us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	15.070s	3.479ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.27295319641655542856246991394651425646659709181689840828781798167829359875238
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  12006316 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  60906316 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  61566316 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  77946316 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  77946316 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1