CHIP Simulation Results

Thursday October 30 2025 17:43:32 UTC

GitHub Revision: `e431c33`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.160m	3.238ms	1	1	100.00
		chip_sw_example_rom	1.385m	2.544ms	1	1	100.00
		chip_sw_example_manufacturer	2.498m	3.135ms	1	1	100.00
		chip_sw_example_concurrency	1.876m	3.136ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.232m	4.944ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.465m	6.314ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.984m	8.631ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.219h	36.081ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	5.821m	6.170ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.219h	36.081ms	1	1	100.00
		chip_csr_rw	5.465m	6.314ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.320s	36.018us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.845m	3.582ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.845m	3.582ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.845m	3.582ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.752m	3.757ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.752m	3.757ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.806m	4.539ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.593m	4.237ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.016m	4.116ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.390m	12.655ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.913m	8.668ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.263m	4.698ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.696m	5.030ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.696m	5.030ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.023m	3.095ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.112m	2.728ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.892m	3.384ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.615m	2.854ms	1	1	100.00
		chip_tap_straps_testunlock0	4.328m	4.830ms	1	1	100.00
		chip_tap_straps_rma	3.496m	4.052ms	1	1	100.00
		chip_tap_straps_prod	1.680m	2.606ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.178m	2.662ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.978m	8.753ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.915m	5.793ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.915m	5.793ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.051m	8.507ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	38.023m	22.698ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.615m	4.685ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.848m	5.794ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.193m	19.196ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.694m	3.177ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.896m	6.813ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.168m	2.428ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.895m	9.905ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.359m	3.644ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.330m	5.094ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.329m	2.770ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.380m	3.415ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.820m	6.535ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.584m	5.485ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.942m	3.223ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.584m	5.485ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.918m	2.362ms	1	1	100.00
		chip_sw_aes_smoketest	3.212m	2.513ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.837m	3.055ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.086m	2.262ms	1	1	100.00
		chip_sw_csrng_smoketest	1.666m	2.348ms	1	1	100.00
		chip_sw_entropy_src_smoketest	10.527m	5.789ms	1	1	100.00
		chip_sw_gpio_smoketest	2.170m	2.498ms	1	1	100.00
		chip_sw_hmac_smoketest	3.127m	3.180ms	1	1	100.00
		chip_sw_kmac_smoketest	2.871m	2.638ms	1	1	100.00
		chip_sw_otbn_smoketest	12.162m	6.753ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.309m	5.746ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.021m	6.099ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.312m	2.264ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.030m	2.609ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.945m	2.971ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.033m	2.853ms	1	1	100.00
		chip_sw_uart_smoketest	2.753m	2.878ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.942m	2.749ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.535m	4.821ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.171h	60.560ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.799m	16.192ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.577m	5.629ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.604m	2.850ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.952m	3.102ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.922h	54.420ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.976h	57.396ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.068m	2.786ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.068m	2.786ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.219h	36.081ms	1	1	100.00
		chip_same_csr_outstanding	18.430m	14.511ms	1	1	100.00
		chip_csr_hw_reset	2.232m	4.944ms	1	1	100.00
		chip_csr_rw	5.465m	6.314ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.219h	36.081ms	1	1	100.00
		chip_same_csr_outstanding	18.430m	14.511ms	1	1	100.00
		chip_csr_hw_reset	2.232m	4.944ms	1	1	100.00
		chip_csr_rw	5.465m	6.314ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	12.840s	541.934us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.700s	52.591us	1	1	100.00
		xbar_smoke_large_delays	53.630s	8.608ms	1	1	100.00
		xbar_smoke_slow_rsp	49.450s	5.720ms	1	1	100.00
		xbar_random_zero_delays	28.570s	537.203us	1	1	100.00
		xbar_random_large_delays	1.447m	14.179ms	1	1	100.00
		xbar_random_slow_rsp	2.380m	15.939ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	5.010s	77.005us	1	1	100.00
		xbar_error_and_unmapped_addr	25.390s	934.182us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	29.210s	1.441ms	1	1	100.00
		xbar_error_and_unmapped_addr	25.390s	934.182us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	12.460s	496.399us	1	1	100.00
		xbar_access_same_device_slow_rsp	10.531m	71.325ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	23.680s	1.344ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	49.010s	2.701ms	1	1	100.00
		xbar_stress_all_with_error	34.650s	695.696us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.198m	509.189us	1	1	100.00
		xbar_stress_all_with_reset_error	9.048m	21.361ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.799m	16.192ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.617m	26.638ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.660m	14.562ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.055m	12.981ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.871m	15.135ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.299m	16.673ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.526m	15.632ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.953m	15.973ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	29.550s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.780s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.970s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	18.020s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	18.070s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.100s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.430s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	19.070s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	24.300s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.990s	10.160us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.350s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.470s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	24.250s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.350s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.760s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.630s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.570s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.770s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	21.170s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.340s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.050s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.530s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.500s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.930s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.850s	10.200us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.815m	11.311ms	1	1	100.00
		rom_e2e_asm_init_dev	41.989m	16.347ms	1	1	100.00
		rom_e2e_asm_init_prod	43.044m	15.043ms	1	1	100.00
		rom_e2e_asm_init_prod_end	43.341m	16.085ms	1	1	100.00
		rom_e2e_asm_init_rma	40.837m	16.516ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	38.405m	16.132ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.809m	16.085ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.370m	16.047ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	39.932m	16.230ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.194m	34.453ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.194m	34.453ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.542m	2.780ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.694m	3.177ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.170m	2.730ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.542m	3.123ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	19.073m	9.059ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.716m	2.407ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.255m	4.510ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.069m	4.507ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.027m	5.514ms	1	1	100.00
		chip_plic_all_irqs_10	4.814m	3.487ms	1	1	100.00
		chip_plic_all_irqs_20	6.218m	4.740ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.996m	2.727ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	20.012m	12.811ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.517m	3.267ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.989m	3.307ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.894m	7.925ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.059m	7.813ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.333m	7.996ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.120h	255.164ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.501m	3.891ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.309m	5.746ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.501m	3.891ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.747m	7.563ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.747m	7.563ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.386m	7.058ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.894m	5.681ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.597m	5.569ms	1	1	100.00
		chip_sw_aes_idle	2.542m	3.123ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.708m	3.517ms	1	1	100.00
		chip_sw_kmac_idle	2.347m	2.396ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.110m	4.338ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.122m	4.968ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.420m	3.703ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.340m	3.044ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	14.340m	10.852ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.751m	4.548ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.911m	4.048ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.015m	3.832ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.041m	5.317ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.641m	4.280ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.659m	4.858ms	1	1	100.00
		chip_sw_ast_clk_outputs	11.051m	8.507ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	8.083m	10.452ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.015m	3.832ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.041m	5.317ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.615m	4.685ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.848m	5.794ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.193m	19.196ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.694m	3.177ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.896m	6.813ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.168m	2.428ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.895m	9.905ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.359m	3.644ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.330m	5.094ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.329m	2.770ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.645m	2.597ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	7.315m	4.816ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.476m	7.076ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.936m	24.708ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.269m	3.107ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.273m	2.983ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.219m	9.232ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.967m	3.625ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.312m	4.106ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.603m	18.679ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.382h	144.934ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.051m	8.507ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.706m	4.599ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.205m	3.066ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.069m	4.507ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	15.894m	7.925ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.127m	5.973ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.646m	2.402ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.838m	6.533ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.380m	2.618ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	37.020m	13.514ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.199m	2.814ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.866m	5.683ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.199m	2.814ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.127m	5.973ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.093m	3.039ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	22.388m	23.997ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.070m	5.601ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.848m	5.794ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.863m	3.895ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.615m	4.685ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	58.801m	43.693ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	22.388m	23.997ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.393m	3.182ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	17.583m	8.595ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.380m	4.598ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	58.801m	43.693ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.380m	4.598ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.380m	4.598ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.380m	4.598ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.380m	4.598ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.069m	4.507ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.678m	8.265ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.973m	5.085ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.310m	4.637ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.310m	4.637ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.097m	2.762ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.168m	2.428ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.708m	3.517ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.202m	3.362ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.640m	4.186ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.324m	4.936ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.692m	5.474ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.157m	5.343ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.615m	3.522ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	17.583m	8.595ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.895m	9.905ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	20.072m	9.583ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	19.073m	9.059ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	44.895m	15.146ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.144m	2.765ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.017m	3.014ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.359m	3.644ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	17.583m	8.595ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.983m	2.819ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.116m	7.971ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.347m	2.396ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.255m	4.510ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.615m	2.854ms	1	1	100.00
		chip_tap_straps_rma	3.496m	4.052ms	1	1	100.00
		chip_tap_straps_prod	1.680m	2.606ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.488m	3.068ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	24.693m	10.564ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.380m	4.598ms	1	1	100.00
		chip_sw_flash_rma_unlocked	58.801m	43.693ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.345m	3.200ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.885m	6.277ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.427m	5.727ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.603m	6.154ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.583m	8.595ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.532m	8.733ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.992m	9.121ms	1	1	100.00
		chip_prim_tl_access	3.678m	8.265ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	8.083m	10.452ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.751m	4.548ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.911m	4.048ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.015m	3.832ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.041m	5.317ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.641m	4.280ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.659m	4.858ms	1	1	100.00
		chip_tap_straps_dev	1.615m	2.854ms	1	1	100.00
		chip_tap_straps_rma	3.496m	4.052ms	1	1	100.00
		chip_tap_straps_prod	1.680m	2.606ms	1	1	100.00
		chip_rv_dm_lc_disabled	57.790s	2.567ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.811m	3.101ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.509m	2.613ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.642m	3.389ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.206m	3.565ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.646m	32.933ms	1	1	100.00
		chip_rv_dm_lc_disabled	57.790s	2.567ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.022h	50.410ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.036h	48.323ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.112m	9.708ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.061h	48.014ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.646m	32.933ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.501m	2.696ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.126m	2.562ms	1	1	100.00
		rom_volatile_raw_unlock	1.041m	2.290ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.601m	16.829ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.193m	19.196ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.597m	5.569ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.597m	5.569ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.597m	5.569ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.526m	3.458ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	22.388m	23.997ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.526m	3.458ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.583m	8.595ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.472m	4.205ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.670m	2.548ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	22.388m	23.997ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.526m	3.458ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.583m	8.595ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.472m	4.205ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.670m	2.548ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.649m	5.633ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.488m	3.068ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.345m	3.200ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.885m	6.277ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.427m	5.727ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.603m	6.154ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.395m	6.518ms	1	1	100.00
		chip_prim_tl_access	3.678m	8.265ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.678m	8.265ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.136m	9.373ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.361m	6.820ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.333m	23.633ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.799m	8.319ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.300m	6.236ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.078m	5.833ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.262m	26.302ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	6.864m	10.147ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	4.747m	7.563ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	9.696m	11.904ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.154m	4.223ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.361m	6.820ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.037m	4.545ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	22.094m	25.175ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.949m	6.810ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.368m	5.397ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.144m	21.339ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.666m	8.354ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.253m	10.200ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	24.732m	27.434ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.761m	2.936ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.069m	4.507ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.532m	8.733ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.532m	8.733ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.253m	10.200ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.144m	21.339ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.154m	4.223ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.309m	5.746ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.027m	4.884ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.724m	3.683ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.150m	4.380ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	20.012m	12.811ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.172m	2.628ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.069m	4.507ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.059m	7.813ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.692m	4.553ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.067m	4.329ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.102m	3.002ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.670m	2.548ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.724m	3.683ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.724m	3.683ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	25.473m	20.512ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.407m	13.038ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.027m	4.884ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.550m	4.164ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.137m	6.789ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.496m	4.052ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	57.790s	2.567ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.027m	5.514ms	1	1	100.00
		chip_plic_all_irqs_10	4.814m	3.487ms	1	1	100.00
		chip_plic_all_irqs_20	6.218m	4.740ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.495m	3.189ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.598m	3.252ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.799m	16.192ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.814m	5.490ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.047m	2.519ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.728m	2.852ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.846m	2.808ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.472m	4.205ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.330m	5.094ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.731m	7.690ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.981m	7.990ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.992m	9.121ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.069m	4.507ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.915m	5.793ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.666m	8.354ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.507m	24.429ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	3.119m	3.203ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.357m	3.782ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.270m	4.377ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.507m	24.429ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.507m	24.429ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	43.132m	20.037ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	43.132m	20.037ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.676m	5.614ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.194m	34.453ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.559m	2.756ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.059m	2.498ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.156m	3.881ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.310m	4.004ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.928m	7.891ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.361h	31.497ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.405m	12.466ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.343m	2.458ms	1	1	100.00
V2		TOTAL			232	275	84.36
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.274m	2.490ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.516m	2.733ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.565h	71.352ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.550m	6.754ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	8.340m	14.449ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.640m	3.835ms	0	1	0.00
		rom_e2e_jtag_debug_rma	3.333m	4.749ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.785m	4.124ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.483m	4.501ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.443m	4.741ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.013s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.726m	5.560ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.737m	2.939ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.510m	3.938ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.975m	6.608ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.316m	2.508ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.845m	5.686ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.080m	2.056ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.402m	2.818ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.906m	5.068ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.976m	3.888ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.253m	10.200ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	8.340m	14.449ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.640m	3.835ms	0	1	0.00
		rom_e2e_jtag_debug_rma	3.333m	4.749ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.359m	4.617ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.069m	4.507ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.541h	38.124ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.541h	38.124ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.800m	3.729ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.752m	3.757ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	54.209m	18.824ms	1	1	100.00
V3		TOTAL			18	23	78.26
	Unmapped tests	chip_sival_flash_info_access	2.284m	2.410ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.112m	4.246ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	35.465m	34.556ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.271m	3.007ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.453m	3.193ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.594m	3.647ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.634s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.045m	3.415ms	1	1	100.00
		TOTAL			275	326	84.36

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.12547378603305711248845811915505655076023344416625608858546086315973006013301
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.67995076091712782484323333730718752969120513951839519242467409044109112658778
    Line 518, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.98007001577811407856088699118602534676713465011848764463565375616043734226950
    Line 522, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.97200671563272814517924249285194915772991384814266255527845879272489778703248
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.18423925438976321560300659688123191136063376389065876483938998917791784066167
    Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.82992633531721105616269119072407159494229497680238739093163546035378435370564
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.89276663576188393790194384784010619019213498762223800736842276022996915502554
    Line 475, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.46500455312265467011707789508071411527137498261352047237082231454931489045354
    Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.77714519554025160732069218324821897524078662267615474977793078900218944924325
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.108264362939707971641039978380916420941653668558750888636462675724830157555152
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.22156015869688420672639927019003216173350522482545187513690123779568889604206
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 10146.695000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 10146.695000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.22026705018300290603779709447619098842260858782233240032270684922546067972604
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6235.731500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6235.731500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.87556094211541670374297266368224548432142326170730678586102351569391504126111
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7563.320000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7563.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.32430992013488714485731232618150224361978125515987049336800313293502658756902
    Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.4483168130678039759085017893704099931572464616705690729646419496598634311310
    Line 484, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.94813851913122743775209129892193469399033709884399530290708527554818466531198
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.8006407631800656398507877901701161032723170984487443363050685929797069573716
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2817.973956 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2817.973956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.24027563877066667989538381561345411822996342646793962349252033829058972582399
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2401.762740 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2401.762740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.2489293321467103607594588880892151842133355280845941434971401053377157521386
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.200s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.42818089128785121283762451474224597671666753944500868599125292699962292685965
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.149s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.51491539287194378837672810655429254709121428678802719009777014879104232880143
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.114236951732079655897765914582909189629018687861303380089330654100577388863470
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.108103484000911249392082099968090256125358047961725327041963955409618553236751
    Line 546, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.73404741395958441570666677502798214820990668304543657627122832385217637438351
    Line 466, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.45619618696627544695225743799435132253249864108076423359720321832225671755926
    Line 602, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3094.787500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3094.787500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.102044698024263309275199357852227470662344563235400968018754987892130071992697
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2519.194680 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2519.194680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.29478854547892176847934657380482554188517045523471346103348276964429518529708
    Line 421, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6153.994380 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6153.994380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.92858411580570725672979102500081144607563592612410426666838295655396011783020
    Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 34555.686506 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 34555.686506 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@91982) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.85655370336742131952316321405812873177985723981835781134235521293523990347101
Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3683.033243 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@91982) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.033243 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1843092126145943660131358880184949287280722699297056088542090575247854440650
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34452.992710 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34452.992710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.48920694014943258697730721215517383625732296675317294016917940891896045057951
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2407.211134 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2407.211134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.88482956048333860980099810766506356186252139717838827683460031604968849808973
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3307.148536 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3307.148536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.57850827862897367056377098964303197935320126312701585857906465793556694547075
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.10752495838261049646626561631715235544221662921780205087687689861499106211767
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3362.059994 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3362.059994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32872) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.767758276467679613967634320663216734751429289491666216177953152726354810873
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2786.474025 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32872) { a_addr: 'h104e0  a_data: 'h358f26  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h19545  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2786.474025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.69558856512004287846047593846928851027848913463521709920027694356748837955586
    Line 198, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 2566.685205 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x107e8 read out mismatch
  UVM_INFO @ 2566.685205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.10523898297336552077813382953578740268150267824189700990022559101195166325334
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2733.474790 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2733.474790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.20954897506005391519472905950044201265028733026320525349207264391140551436676
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2850.088000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2850.088000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.4889090382240890793600641031001318924264714521127545616839426952024142924916
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3101.850000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3101.850000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.82025720376276862347455901323350603796781823869271610169861365726406863703408
    Line 432, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 22698.059084 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 22698.059084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.99338129311375853655191002220355224460130919538377546950529569082113729796188
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.100678364089170428220651098033834721076213107377338863964352743862673216850627
    Line 469, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.4340278913275248664810169403137187002767328717160288682548445821450471524832
    Line 428, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 14449.083371 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 14449.083371 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.104396581001798037344021600383348150041658004028743252389236239736015783711598
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 3834.963970 us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 3834.963970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.13321963299707217027102966181425060594728139863261070157856661600215876278349
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_ERROR @ 4748.611650 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4748.611650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```