ADC_CTRL Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.550s	5.611ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.870s	708.209us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.880s	490.171us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	39.020s	52.656ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.210s	530.966us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.510s	430.618us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.880s	490.171us	1	1	100.00
		adc_ctrl_csr_aliasing	3.210s	530.966us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	14.433m	493.989ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.077m	162.103ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1.090m	157.457ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	5.275m	168.609ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.876m	198.988ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.482m	207.294ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	7.587m	491.474ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.811m	328.868ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.890s	4.489ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	35.540s	44.693ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.546m	129.114ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	9.991m	367.182ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.920s	325.255us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.750s	480.435us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.210s	325.657us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.210s	325.657us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.870s	708.209us	1	1	100.00
		adc_ctrl_csr_rw	1.880s	490.171us	1	1	100.00
		adc_ctrl_csr_aliasing	3.210s	530.966us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.460s	2.293ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.870s	708.209us	1	1	100.00
		adc_ctrl_csr_rw	1.880s	490.171us	1	1	100.00
		adc_ctrl_csr_aliasing	3.210s	530.966us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.460s	2.293ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.410s	3.999ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.660s	4.361ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.660s	4.361ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	22.780s	5.784ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00