EDN Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.320s 18.392us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.000s 13.766us 1 1 100.00
V1 csr_rw edn_csr_rw 1.070s 37.128us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.470s 1.653ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.630s 415.456us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.620s 43.381us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.070s 37.128us 1 1 100.00
edn_csr_aliasing 1.630s 415.456us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.520s 38.340us 1 1 100.00
V2 csrng_commands edn_genbits 1.520s 38.340us 1 1 100.00
V2 genbits edn_genbits 1.520s 38.340us 1 1 100.00
V2 interrupts edn_intr 0.790s 33.618us 1 1 100.00
V2 alerts edn_alert 1.450s 23.451us 1 1 100.00
V2 errs edn_err 0.860s 29.114us 1 1 100.00
V2 disable edn_disable 0.810s 56.006us 1 1 100.00
edn_disable_auto_req_mode 0.900s 91.049us 1 1 100.00
V2 stress_all edn_stress_all 2.560s 842.575us 1 1 100.00
V2 intr_test edn_intr_test 1.010s 12.485us 1 1 100.00
V2 alert_test edn_alert_test 1.110s 15.030us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.870s 45.784us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.870s 45.784us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.000s 13.766us 1 1 100.00
edn_csr_rw 1.070s 37.128us 1 1 100.00
edn_csr_aliasing 1.630s 415.456us 1 1 100.00
edn_same_csr_outstanding 1.290s 57.275us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.000s 13.766us 1 1 100.00
edn_csr_rw 1.070s 37.128us 1 1 100.00
edn_csr_aliasing 1.630s 415.456us 1 1 100.00
edn_same_csr_outstanding 1.290s 57.275us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.520s 4.885ms 1 1 100.00
edn_tl_intg_err 1.930s 280.905us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.090s 24.729us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.450s 23.451us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.520s 4.885ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.520s 4.885ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.520s 4.885ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.520s 4.885ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.450s 23.451us 1 1 100.00
edn_sec_cm 7.520s 4.885ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.450s 23.451us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.930s 280.905us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets