ENTROPY_SRC/RNG_4BITS Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 3.000s 50.542us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 2.000s 155.470us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 2.000s 32.459us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 7.000s 220.124us 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 516.296us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 2.000s 40.669us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 2.000s 32.459us 1 1 100.00
entropy_src_csr_aliasing 6.000s 516.296us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 3.000s 50.542us 1 1 100.00
entropy_src_rng 1.300m 10.142ms 1 1 100.00
entropy_src_fw_ov 11.000s 10.214ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 11.000s 10.214ms 1 1 100.00
V2 rng_mode entropy_src_rng 1.300m 10.142ms 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 2.067m 18.170ms 1 1 100.00
V2 health_checks entropy_src_rng 1.300m 10.142ms 1 1 100.00
V2 conditioning entropy_src_rng 1.300m 10.142ms 1 1 100.00
V2 interrupts entropy_src_rng 1.300m 10.142ms 1 1 100.00
entropy_src_intr 10.000s 995.894us 1 1 100.00
V2 alerts entropy_src_rng 1.300m 10.142ms 1 1 100.00
entropy_src_functional_alerts 10.000s 187.889us 1 1 100.00
V2 stress_all entropy_src_stress_all 0 1 0.00
V2 functional_errors entropy_src_functional_errors 3.000s 798.338us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 2.000s 515.353us 1 1 100.00
V2 intr_test entropy_src_intr_test 2.000s 15.292us 1 1 100.00
V2 alert_test entropy_src_alert_test 2.000s 79.640us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 4.000s 101.824us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 4.000s 101.824us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 2.000s 155.470us 1 1 100.00
entropy_src_csr_rw 2.000s 32.459us 1 1 100.00
entropy_src_csr_aliasing 6.000s 516.296us 1 1 100.00
entropy_src_same_csr_outstanding 7.000s 56.209us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 2.000s 155.470us 1 1 100.00
entropy_src_csr_rw 2.000s 32.459us 1 1 100.00
entropy_src_csr_aliasing 6.000s 516.296us 1 1 100.00
entropy_src_same_csr_outstanding 7.000s 56.209us 1 1 100.00
V2 TOTAL 11 12 91.67
V2S tl_intg_err entropy_src_sec_cm 3.000s 102.383us 1 1 100.00
entropy_src_tl_intg_err 3.000s 66.254us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 1.300m 10.142ms 1 1 100.00
entropy_src_cfg_regwen 2.000s 13.994us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 1.300m 10.142ms 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 1.300m 10.142ms 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 1.300m 10.142ms 1 1 100.00
entropy_src_fw_ov 11.000s 10.214ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 3.000s 798.338us 1 1 100.00
entropy_src_sec_cm 3.000s 102.383us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 3.000s 798.338us 1 1 100.00
entropy_src_sec_cm 3.000s 102.383us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 1.300m 10.142ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 3.000s 798.338us 1 1 100.00
entropy_src_sec_cm 3.000s 102.383us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 3.000s 798.338us 1 1 100.00
entropy_src_sec_cm 3.000s 102.383us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 3.000s 798.338us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 10.000s 187.889us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 3.000s 66.254us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 1.417m 19.068ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 21 22 95.45

Failure Buckets