HMAC Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.630s 5.659ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.700s 22.917us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.760s 17.275us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.340s 1.277ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.560s 259.157us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 6.919m 254.338ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.760s 17.275us 1 1 100.00
hmac_csr_aliasing 2.560s 259.157us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.039m 9.117ms 1 1 100.00
V2 back_pressure hmac_back_pressure 54.840s 5.704ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.023m 19.817ms 1 1 100.00
hmac_test_sha384_vectors 20.000s 302.338us 1 1 100.00
hmac_test_sha512_vectors 20.420s 521.192us 1 1 100.00
hmac_test_hmac256_vectors 7.570s 973.401us 1 1 100.00
hmac_test_hmac384_vectors 7.770s 1.118ms 1 1 100.00
hmac_test_hmac512_vectors 9.980s 411.537us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.190s 1.407ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.013m 3.882ms 1 1 100.00
V2 error hmac_error 1.158m 20.055ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.440m 7.041ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.630s 5.659ms 1 1 100.00
hmac_long_msg 1.039m 9.117ms 1 1 100.00
hmac_back_pressure 54.840s 5.704ms 1 1 100.00
hmac_datapath_stress 4.013m 3.882ms 1 1 100.00
hmac_burst_wr 18.190s 1.407ms 1 1 100.00
hmac_stress_all 7.030s 697.724us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.630s 5.659ms 1 1 100.00
hmac_long_msg 1.039m 9.117ms 1 1 100.00
hmac_back_pressure 54.840s 5.704ms 1 1 100.00
hmac_datapath_stress 4.013m 3.882ms 1 1 100.00
hmac_wipe_secret 1.440m 7.041ms 1 1 100.00
hmac_test_sha256_vectors 3.023m 19.817ms 1 1 100.00
hmac_test_sha384_vectors 20.000s 302.338us 1 1 100.00
hmac_test_sha512_vectors 20.420s 521.192us 1 1 100.00
hmac_test_hmac256_vectors 7.570s 973.401us 1 1 100.00
hmac_test_hmac384_vectors 7.770s 1.118ms 1 1 100.00
hmac_test_hmac512_vectors 9.980s 411.537us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.630s 5.659ms 1 1 100.00
hmac_long_msg 1.039m 9.117ms 1 1 100.00
hmac_back_pressure 54.840s 5.704ms 1 1 100.00
hmac_datapath_stress 4.013m 3.882ms 1 1 100.00
hmac_burst_wr 18.190s 1.407ms 1 1 100.00
hmac_error 1.158m 20.055ms 1 1 100.00
hmac_wipe_secret 1.440m 7.041ms 1 1 100.00
hmac_test_sha256_vectors 3.023m 19.817ms 1 1 100.00
hmac_test_sha384_vectors 20.000s 302.338us 1 1 100.00
hmac_test_sha512_vectors 20.420s 521.192us 1 1 100.00
hmac_test_hmac256_vectors 7.570s 973.401us 1 1 100.00
hmac_test_hmac384_vectors 7.770s 1.118ms 1 1 100.00
hmac_test_hmac512_vectors 9.980s 411.537us 1 1 100.00
hmac_stress_all 7.030s 697.724us 1 1 100.00
V2 stress_all hmac_stress_all 7.030s 697.724us 1 1 100.00
V2 alert_test hmac_alert_test 0.850s 17.604us 1 1 100.00
V2 intr_test hmac_intr_test 0.660s 88.023us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.020s 469.291us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.020s 469.291us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.700s 22.917us 1 1 100.00
hmac_csr_rw 0.760s 17.275us 1 1 100.00
hmac_csr_aliasing 2.560s 259.157us 1 1 100.00
hmac_same_csr_outstanding 1.290s 40.555us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.700s 22.917us 1 1 100.00
hmac_csr_rw 0.760s 17.275us 1 1 100.00
hmac_csr_aliasing 2.560s 259.157us 1 1 100.00
hmac_same_csr_outstanding 1.290s 40.555us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.040s 1.086ms 1 1 100.00
hmac_tl_intg_err 4.150s 1.026ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.150s 1.026ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.630s 5.659ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.600s 255.490us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.517m 7.438ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.880s 46.780us 1 1 100.00
TOTAL 28 28 100.00