I2C Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	17.950s	1.765ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.410s	3.571ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.710s	72.825us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.710s	40.190us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.960s	195.654us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.420s	94.890us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.770s	67.413us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.710s	40.190us	1	1	100.00
		i2c_csr_aliasing	1.420s	94.890us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.960s	172.509us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	8.163m	9.870ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	56.320s	5.369ms	1	1	100.00
V2	host_override	i2c_host_override	0.640s	26.397us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	43.970s	11.327ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	22.510s	5.227ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.830s	373.337us	1	1	100.00
		i2c_host_fifo_fmt_empty	13.300s	1.813ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.400s	142.768us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.653m	15.313ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.990s	1.419ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.860s	435.150us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.720s	449.967us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	11.566m	56.409ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.740s	1.392ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	4.300s	1.466ms	1	1	100.00
		i2c_target_intr_smoke	3.420s	1.872ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.180s	149.888us	1	1	100.00
		i2c_target_fifo_reset_tx	1.450s	308.877us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.577m	42.780ms	1	1	100.00
		i2c_target_stress_rd	4.300s	1.466ms	1	1	100.00
		i2c_target_intr_stress_wr	3.900s	11.477ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.420s	4.663ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	12.960s	5.031ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.370s	607.583us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	20.540s	10.122ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.380s	239.981us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.800s	2.645ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	56.320s	5.369ms	1	1	100.00
		i2c_host_perf_precise	21.800s	795.144us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.990s	1.419ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.390s	136.965us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.180s	2.100ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.920s	1.202ms	1	1	100.00
		i2c_target_nack_txstretch	1.040s	135.526us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	18.170s	2.542ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.730s	2.047ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.680s	57.130us	1	1	100.00
V2	intr_test	i2c_intr_test	0.710s	28.792us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.460s	143.140us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.460s	143.140us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.710s	72.825us	1	1	100.00
		i2c_csr_rw	0.710s	40.190us	1	1	100.00
		i2c_csr_aliasing	1.420s	94.890us	1	1	100.00
		i2c_same_csr_outstanding	0.930s	48.322us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.710s	72.825us	1	1	100.00
		i2c_csr_rw	0.710s	40.190us	1	1	100.00
		i2c_csr_aliasing	1.420s	94.890us	1	1	100.00
		i2c_same_csr_outstanding	0.930s	48.322us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.150s	297.224us	1	1	100.00
		i2c_sec_cm	1.030s	111.438us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.150s	297.224us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	7.330s	1.041ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.750s	182.426us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.760s	411.688us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.90960409646158346810429721576187878937733839440364986807165712398657243992008
      Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 172509194 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 172509194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.61467006765044096725276801654111659043539382024046703580446671013923381711377
      Line 130, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 9870128138 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 9870128138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.1687565471050911029085099858774679762229149595122827972727998184993017486914
      Line 132, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1041123055 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1041123055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.29409055918335954194443205757555196824605101245727337871909128626484905436971
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 411688401 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 411688401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.10532527953834749497481371503281715035772001737014994278969432992931939964181
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 449966866 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 449966866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.78144268263647873743072428393933680163775386636149493462224986704756365240964
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 182425699 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 194 [0xc2])
        UVM_INFO @ 182425699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.21555339330175003521646959702463297630154227498351537193722153504215823265767
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10122161758 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10122161758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.51960061319989969185879994458595341093642665743557028793894909241729158143788
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 435150275 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @14416