KEYMGR Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.640s	33.008us	1	1	100.00
V1	random	keymgr_random	4.170s	177.741us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.970s	128.276us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.910s	18.567us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.750s	3.897ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.180s	400.343us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.190s	40.204us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.910s	18.567us	1	1	100.00
		keymgr_csr_aliasing	3.180s	400.343us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.450s	66.644us	1	1	100.00
V2	sideload	keymgr_sideload	4.780s	881.161us	1	1	100.00
		keymgr_sideload_kmac	3.000s	156.868us	1	1	100.00
		keymgr_sideload_aes	2.120s	230.939us	1	1	100.00
		keymgr_sideload_otbn	2.000s	152.639us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.970s	269.566us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.240s	56.685us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.110s	322.830us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.710s	133.855us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.300s	113.381us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	6.100s	423.226us	1	1	100.00
V2	stress_all	keymgr_stress_all	15.730s	939.507us	0	1	0.00
V2	intr_test	keymgr_intr_test	0.750s	93.055us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.730s	10.774us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.610s	370.963us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.610s	370.963us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.970s	128.276us	1	1	100.00
		keymgr_csr_rw	0.910s	18.567us	1	1	100.00
		keymgr_csr_aliasing	3.180s	400.343us	1	1	100.00
		keymgr_same_csr_outstanding	1.280s	228.215us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.970s	128.276us	1	1	100.00
		keymgr_csr_rw	0.910s	18.567us	1	1	100.00
		keymgr_csr_aliasing	3.180s	400.343us	1	1	100.00
		keymgr_same_csr_outstanding	1.280s	228.215us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
		keymgr_tl_intg_err	2.070s	78.854us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.000s	78.685us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.000s	78.685us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.000s	78.685us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.000s	78.685us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.450s	818.808us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.070s	78.854us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.000s	78.685us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.450s	66.644us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.170s	177.741us	1	1	100.00
		keymgr_csr_rw	0.910s	18.567us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.170s	177.741us	1	1	100.00
		keymgr_csr_rw	0.910s	18.567us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.170s	177.741us	1	1	100.00
		keymgr_csr_rw	0.910s	18.567us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.240s	56.685us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.300s	113.381us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.300s	113.381us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.170s	177.741us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.050s	88.500us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.470s	281.007us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.240s	56.685us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.470s	281.007us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.470s	281.007us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.470s	281.007us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.690s	3.195ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.470s	281.007us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.040s	326.544us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
  • Test keymgr_stress_all has 1 failures.

    • 0.keymgr_stress_all.7042651849461158673503856194479988701666574056743071228178857853773271475266
      Line 437, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 939507333 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_5
        UVM_INFO @ 939507333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---