KMAC/UNMASKED Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	21.310s	2.856ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.900s	58.615us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.890s	23.476us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.440s	1.132ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.240s	80.017us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.810s	40.104us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.890s	23.476us	1	1	100.00
		kmac_csr_aliasing	3.240s	80.017us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.680s	55.488us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.070s	53.529us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	15.148m	147.742ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.950s	537.260us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	19.058m	72.190ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.296m	119.932ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.366m	726.985ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.513m	9.552ms	1	1	100.00
		kmac_test_vectors_shake_128	27.912m	69.004ms	1	1	100.00
		kmac_test_vectors_shake_256	3.535m	24.594ms	1	1	100.00
		kmac_test_vectors_kmac	1.600s	310.454us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.960s	95.338us	1	1	100.00
V2	sideload	kmac_sideload	1.388m	1.627ms	1	1	100.00
V2	app	kmac_app	57.660s	2.506ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	30.030s	7.157ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.441m	9.103ms	1	1	100.00
V2	error	kmac_error	3.940m	11.996ms	1	1	100.00
V2	key_error	kmac_key_error	1.770s	1.139ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.550s	556.284us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	11.350s	624.093us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	10.160s	1.005ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	44.530s	7.976ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.470s	120.428us	1	1	100.00
V2	stress_all	kmac_stress_all	1.293m	1.305ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.850s	55.654us	1	1	100.00
V2	alert_test	kmac_alert_test	0.850s	51.691us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.380s	139.583us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.380s	139.583us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.900s	58.615us	1	1	100.00
		kmac_csr_rw	0.890s	23.476us	1	1	100.00
		kmac_csr_aliasing	3.240s	80.017us	1	1	100.00
		kmac_same_csr_outstanding	1.260s	87.070us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.900s	58.615us	1	1	100.00
		kmac_csr_rw	0.890s	23.476us	1	1	100.00
		kmac_csr_aliasing	3.240s	80.017us	1	1	100.00
		kmac_same_csr_outstanding	1.260s	87.070us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	82.690us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	82.690us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	82.690us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	82.690us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.590s	321.212us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	46.220s	17.859ms	1	1	100.00
		kmac_tl_intg_err	2.360s	156.321us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.360s	156.321us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.470s	120.428us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	21.310s	2.856ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.388m	1.627ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	82.690us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	46.220s	17.859ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	46.220s	17.859ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	46.220s	17.859ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	21.310s	2.856ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.470s	120.428us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	46.220s	17.859ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.248m	200.000ms	0	1	0.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	21.310s	2.856ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.067m	3.780ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_mubi has 1 failures.

    • 0.kmac_mubi.78720961448587317588724166816272163847318367103881263902128988319257021142375
      Line 229, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mubi/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.28921440510049017967574092951534741748519528157098199661537197948812633567573
      Line 334, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3779932582 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3779932582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---