PATTGEN Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: `7f2e68c`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	86.869us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	20.645us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	12.700us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	499.596us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	46.742us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	16.544us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	12.700us	1	1	100.00
		pattgen_csr_aliasing	2.000s	46.742us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	8.000s	3.515ms	1	1	100.00
V2	error	pattgen_error	1.000s	42.856us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.000s	383.086us	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	43.545us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	14.570us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	150.970us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	150.970us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	20.645us	1	1	100.00
		pattgen_csr_rw	1.000s	12.700us	1	1	100.00
		pattgen_csr_aliasing	2.000s	46.742us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	42.612us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	20.645us	1	1	100.00
		pattgen_csr_rw	1.000s	12.700us	1	1	100.00
		pattgen_csr_aliasing	2.000s	46.742us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	42.612us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	416.571us	1	1	100.00
		pattgen_sec_cm	2.000s	147.561us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	416.571us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	49.000s	12.552ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	194.863us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

Job timed out after * minutes has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.3122254591571830365761477336341929597968501574709856173302443467065700488924
    Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.4315913229362033283751326767631868330682958802606825598705367754016633510560
Line 236, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4586012459 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4586045702 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4586045702 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 4586337371 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.8956958195284604684725153752488363263953539477786526735864520248846655938292
    Line 158, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 383085532 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10182
```