RV_TIMER Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.580s	16.023us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.570s	16.170us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.600s	28.104us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.670s	64.115us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.610s	26.100us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.590s	85.210us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.600s	28.104us	1	1	100.00
		rv_timer_csr_aliasing	0.610s	26.100us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.900s	412.784us	0	1	0.00
V2	disabled	rv_timer_disabled	1.530s	1.169ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	0.570s	190.324us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	0.570s	190.324us	1	1	100.00
V2	stress	rv_timer_stress_all	0.950s	170.083us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.600s	15.061us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.570s	12.350us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.430s	146.398us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.430s	146.398us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.570s	16.170us	1	1	100.00
		rv_timer_csr_rw	0.600s	28.104us	1	1	100.00
		rv_timer_csr_aliasing	0.610s	26.100us	1	1	100.00
		rv_timer_same_csr_outstanding	0.730s	31.997us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.570s	16.170us	1	1	100.00
		rv_timer_csr_rw	0.600s	28.104us	1	1	100.00
		rv_timer_csr_aliasing	0.610s	26.100us	1	1	100.00
		rv_timer_same_csr_outstanding	0.730s	31.997us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.880s	152.197us	1	1	100.00
		rv_timer_tl_intg_err	0.970s	281.103us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.970s	281.103us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.960s	236.358us	0	1	0.00
V3	max_value	rv_timer_max	0.610s	79.047us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	36.480s	17.643ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.113585161221098819274303989884273929170618520758277691102621672009309342920931
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 236357598 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd8324904) == 0x1
        UVM_INFO @ 236357598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.68849584798860959026641554133580837656383882434807981373246508680057778237483
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 412784043 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc6b13d04) == 0x1
        UVM_INFO @ 412784043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.91847188103743994534377780472295572540028706058281710543214113639668480051621
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  79047178 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  79047178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---