SPI_DEVICE/1R1W Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	32.550s	3.574ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.080s	34.758us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.210s	29.691us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.650s	357.926us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.800s	4.137ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.150s	142.658us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.210s	29.691us	1	1	100.00
		spi_device_csr_aliasing	11.800s	4.137ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.800s	34.011us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.830s	98.042us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.950s	21.550us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	1.558us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	6.888us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.760s	206.896us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.760s	206.896us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.360s	549.820us	1	1	100.00
		spi_device_tpm_sts_read	0.720s	63.576us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	0.640s	141.085us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.970s	1.805ms	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.830s	110.122us	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.830s	110.122us	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.510s	451.341us	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.510s	451.341us	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.510s	451.341us	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.510s	451.341us	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.510s	451.341us	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.800s	6.990ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	24.620s	16.665ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	24.620s	16.665ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	24.620s	16.665ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.270s	704.663us	1	1	100.00
		spi_device_read_buffer_direct	3.730s	300.553us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	24.620s	16.665ms	1	1	100.00
		spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.382m	80.446ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.560s	10.177ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.560s	10.177ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	32.550s	3.574ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.689m	95.185ms	1	1	100.00
V2	stress_all	spi_device_stress_all	5.765m	59.441ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.670s	10.919us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.690s	12.889us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.870s	60.185us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.870s	60.185us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.080s	34.758us	1	1	100.00
		spi_device_csr_rw	1.210s	29.691us	1	1	100.00
		spi_device_csr_aliasing	11.800s	4.137ms	1	1	100.00
		spi_device_same_csr_outstanding	2.160s	43.948us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.080s	34.758us	1	1	100.00
		spi_device_csr_rw	1.210s	29.691us	1	1	100.00
		spi_device_csr_aliasing	11.800s	4.137ms	1	1	100.00
		spi_device_same_csr_outstanding	2.160s	43.948us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.290s	559.383us	1	1	100.00
		spi_device_tl_intg_err	17.310s	3.610ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.310s	3.610ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	41.760s	38.462ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.65069804533520530201082484337395304937244852530616373267527437189566070758169
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    859766 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[23])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    859766 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    859766 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[919])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.42113171915022396908766608326910550478702492678822876014267629451604302798505
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4551738 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x819caf [100000011001110010101111] vs 0x0 [0])
        UVM_ERROR @   4580738 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe8ecf4 [111010001110110011110100] vs 0x0 [0])
        UVM_ERROR @   4598738 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7c2d26 [11111000010110100100110] vs 0x0 [0])
        UVM_ERROR @   4682738 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1ffb63 [111111111101101100011] vs 0x0 [0])
        UVM_ERROR @   4683738 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbf61d6 [101111110110000111010110] vs 0x0 [0])