SPI_DEVICE/2P Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	45.190s	36.630ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.320s	52.449us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.200s	42.627us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.240s	3.127ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.340s	1.080ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.970s	89.727us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.200s	42.627us	1	1	100.00
		spi_device_csr_aliasing	15.340s	1.080ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.770s	30.603us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.350s	183.643us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.880s	17.398us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.000s	56.367us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.680s	15.559us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.220s	99.662us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.220s	99.662us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.470s	2.692ms	1	1	100.00
		spi_device_tpm_sts_read	0.950s	37.156us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.630s	5.589ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.720s	2.552ms	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.790s	11.504ms	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.790s	11.504ms	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.730s	373.981us	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.730s	373.981us	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.730s	373.981us	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.730s	373.981us	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.730s	373.981us	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.840s	86.492us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	10.550s	1.586ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	10.550s	1.586ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	10.550s	1.586ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	30.180s	7.500ms	1	1	100.00
		spi_device_read_buffer_direct	9.940s	4.646ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	10.550s	1.586ms	1	1	100.00
		spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	25.410s	6.015ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.600s	116.818us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.600s	116.818us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	45.190s	36.630ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.747m	128.816ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.042m	43.397ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.710s	11.949us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.700s	12.190us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.220s	820.854us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.220s	820.854us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.320s	52.449us	1	1	100.00
		spi_device_csr_rw	1.200s	42.627us	1	1	100.00
		spi_device_csr_aliasing	15.340s	1.080ms	1	1	100.00
		spi_device_same_csr_outstanding	1.460s	129.186us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.320s	52.449us	1	1	100.00
		spi_device_csr_rw	1.200s	42.627us	1	1	100.00
		spi_device_csr_aliasing	15.340s	1.080ms	1	1	100.00
		spi_device_same_csr_outstanding	1.460s	129.186us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.280s	149.088us	1	1	100.00
		spi_device_tl_intg_err	9.120s	401.211us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.120s	401.211us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	41.610s	2.588ms	1	1	100.00
		TOTAL			33	33	100.00