SPI_HOST Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	20.000s	3.710ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	7.000s	165.359us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	20.718us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	215.100us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	56.706us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	58.146us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	20.718us	1	1	100.00
		spi_host_csr_aliasing	5.000s	56.706us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	9.000s	23.577us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	9.000s	70.563us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	51.537us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	172.441us	1	1	100.00
		spi_host_error_cmd	2.000s	42.867us	1	1	100.00
		spi_host_event	22.000s	3.190ms	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	293.641us	1	1	100.00
V2	speed	spi_host_speed	3.000s	293.641us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	293.641us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	86.597us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	106.061us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	293.641us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	293.641us	1	1	100.00
V2	duplex	spi_host_smoke	20.000s	3.710ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	20.000s	3.710ms	1	1	100.00
V2	stress_all	spi_host_stress_all	3.000s	226.641us	1	1	100.00
V2	spien	spi_host_spien	4.000s	378.176us	1	1	100.00
V2	stall	spi_host_status_stall	7.000s	518.374us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	364.136us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	172.441us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	58.479us	1	1	100.00
V2	intr_test	spi_host_intr_test	9.000s	19.714us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	11.000s	1.569ms	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	11.000s	1.569ms	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	7.000s	165.359us	1	1	100.00
		spi_host_csr_rw	7.000s	20.718us	1	1	100.00
		spi_host_csr_aliasing	5.000s	56.706us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	32.869us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	7.000s	165.359us	1	1	100.00
		spi_host_csr_rw	7.000s	20.718us	1	1	100.00
		spi_host_csr_aliasing	5.000s	56.706us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	32.869us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	9.000s	169.732us	1	1	100.00
		spi_host_sec_cm	2.000s	128.566us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	9.000s	169.732us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.033m	3.465ms	1	1	100.00
		TOTAL			26	26	100.00