SRAM_CTRL/RET Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.760s	3.189ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.820s	12.232us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.850s	31.192us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	483.607us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	17.529us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.830s	30.632us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.850s	31.192us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	17.529us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.010s	147.773us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.220s	97.037us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.130s	637.032us	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.487m	8.906ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	41.360s	2.612ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.250m	4.927ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.640s	1.011ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.428m	49.900ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.280s	1.140ms	1	1	100.00
		sram_ctrl_partial_access_b2b	1.202m	6.464ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.040s	53.574us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	40.950s	1.686ms	1	1	100.00
		sram_ctrl_throughput_w_readback	43.140s	455.246us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.396m	2.421ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.770s	134.159us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	24.808m	48.001ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.980s	33.377us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.560s	78.238us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.560s	78.238us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.820s	12.232us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	31.192us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	17.529us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.810s	18.475us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.820s	12.232us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	31.192us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	17.529us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.810s	18.475us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.350s	1.629ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.680s	3.812us	0	1	0.00
		sram_ctrl_tl_intg_err	1.590s	209.768us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.680s	3.812us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.590s	209.768us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.396m	2.421ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.396m	2.421ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.850s	31.192us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.428m	49.900ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.428m	49.900ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.428m	49.900ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.640s	1.011ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.930s	130.563us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.350s	1.629ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.270s	95.340us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.760s	3.189ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.760s	3.189ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.428m	49.900ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.680s	3.812us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.640s	1.011ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.680s	3.812us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.680s	3.812us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.760s	3.189ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.680s	3.812us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	20.540s	576.320us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.63620180596437388060140341907284650365935354423104241111255854120876089504216
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3812463 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3812463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---