SYSRST_CTRL Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.610s 2.124ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.720s 2.474ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 1.600s 2.150ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.540s 2.334ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 11.090s 6.010ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.850s 2.066ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.187m 38.812ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 2.800s 2.606ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.010s 2.049ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.850s 2.066ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.800s 2.606ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 35.050s 74.475ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 35.960s 44.492ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.510s 3.367ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 3.310s 2.947ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.040s 2.508ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.090s 2.058ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 2.640s 4.332ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.790s 2.630ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 6.300s 9.943ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.291m 38.805ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 1.417m 48.702ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 4.180s 2.013ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.370s 2.026ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.200s 3.134ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.200s 3.134ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 11.090s 6.010ms 1 1 100.00
sysrst_ctrl_csr_rw 3.850s 2.066ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.800s 2.606ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.750s 9.584ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 11.090s 6.010ms 1 1 100.00
sysrst_ctrl_csr_rw 3.850s 2.066ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.800s 2.606ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.750s 9.584ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 19.080s 22.049ms 1 1 100.00
sysrst_ctrl_tl_intg_err 22.010s 22.224ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 22.010s 22.224ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 13.530s 6.721ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00