UART Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.250s	5.444ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.710s	85.295us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.720s	142.659us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.370s	347.366us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.930s	115.957us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.940s	32.551us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.720s	142.659us	1	1	100.00
		uart_csr_aliasing	0.930s	115.957us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	40.980s	36.659ms	1	1	100.00
V2	parity	uart_smoke	7.250s	5.444ms	1	1	100.00
		uart_tx_rx	40.980s	36.659ms	1	1	100.00
V2	parity_error	uart_intr	6.540s	11.055ms	1	1	100.00
		uart_rx_parity_err	1.799m	90.574ms	1	1	100.00
V2	watermark	uart_tx_rx	40.980s	36.659ms	1	1	100.00
		uart_intr	6.540s	11.055ms	1	1	100.00
V2	fifo_full	uart_fifo_full	27.320s	22.653ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	44.520s	101.527ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.166m	144.428ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.540s	11.055ms	1	1	100.00
V2	rx_break_err	uart_intr	6.540s	11.055ms	1	1	100.00
V2	rx_timeout	uart_intr	6.540s	11.055ms	1	1	100.00
V2	perf	uart_perf	2.349m	10.386ms	1	1	100.00
V2	sys_loopback	uart_loopback	8.870s	12.293ms	1	1	100.00
V2	line_loopback	uart_loopback	8.870s	12.293ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	4.850s	18.223ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.360s	5.826ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	17.110s	13.123ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	5.040s	2.433ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.852m	151.864ms	1	1	100.00
V2	stress_all	uart_stress_all	31.040s	260.675ms	0	1	0.00
V2	alert_test	uart_alert_test	0.830s	13.237us	1	1	100.00
V2	intr_test	uart_intr_test	0.590s	19.421us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.330s	65.307us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.330s	65.307us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.710s	85.295us	1	1	100.00
		uart_csr_rw	0.720s	142.659us	1	1	100.00
		uart_csr_aliasing	0.930s	115.957us	1	1	100.00
		uart_same_csr_outstanding	0.940s	339.787us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.710s	85.295us	1	1	100.00
		uart_csr_rw	0.720s	142.659us	1	1	100.00
		uart_csr_aliasing	0.930s	115.957us	1	1	100.00
		uart_same_csr_outstanding	0.940s	339.787us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.210s	157.474us	1	1	100.00
		uart_tl_intg_err	0.880s	178.641us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.880s	178.641us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.910s	51.250ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.72857145088667148078122424655093641981131356000210720469848007192532140238951
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 15948439273 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 15948486892 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 15948534511 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 175 [0xaf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 15948582130 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 15948629749 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.68819842109013676331190748734085218554144812121266324783397688359359137068791
      Line 146, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 252549802602 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 252566358141 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 253018579911 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 253018579911 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 253018579911 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1