CHIP Simulation Results

Monday November 03 2025 17:34:39 UTC

GitHub Revision: `7f2e68c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.171m	2.919ms	1	1	100.00
		chip_sw_example_rom	1.210m	2.193ms	1	1	100.00
		chip_sw_example_manufacturer	1.558m	2.466ms	1	1	100.00
		chip_sw_example_concurrency	2.135m	2.635ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.089m	4.294ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.437m	3.625ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.053m	5.447ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.087h	28.558ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	3.776m	4.980ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.087h	28.558ms	1	1	100.00
		chip_csr_rw	3.437m	3.625ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	9.300s	191.708us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.711m	4.602ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.711m	4.602ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.711m	4.602ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.691m	4.138ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.691m	4.138ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.424m	4.099ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.464m	4.557ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.758m	3.976ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.286m	8.009ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	7.206m	4.460ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.965m	4.079ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.723m	4.550ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.723m	4.550ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.092m	2.256ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.828m	3.050ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.816m	3.742ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	6.291m	6.760ms	1	1	100.00
		chip_tap_straps_testunlock0	1.534m	2.985ms	1	1	100.00
		chip_tap_straps_rma	1.394m	2.531ms	1	1	100.00
		chip_tap_straps_prod	1.787m	3.028ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.130m	3.582ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.277m	9.123ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.478m	6.089ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.478m	6.089ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.364m	7.670ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	27.958m	15.883ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.723m	4.392ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.111m	6.138ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.072m	18.844ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.075m	3.379ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.296m	6.742ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.269m	3.045ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	27.223m	13.757ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.823m	2.742ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.155m	4.957ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.990m	2.987ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.324m	2.763ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	2.546m	2.688ms	0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.679m	5.339ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.114m	3.366ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.679m	5.339ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.655m	2.402ms	1	1	100.00
		chip_sw_aes_smoketest	2.156m	2.422ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.638m	3.024ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.346m	2.831ms	1	1	100.00
		chip_sw_csrng_smoketest	2.112m	3.330ms	1	1	100.00
		chip_sw_entropy_src_smoketest	10.548m	5.765ms	1	1	100.00
		chip_sw_gpio_smoketest	2.964m	3.201ms	1	1	100.00
		chip_sw_hmac_smoketest	2.778m	2.753ms	1	1	100.00
		chip_sw_kmac_smoketest	3.272m	2.824ms	1	1	100.00
		chip_sw_otbn_smoketest	15.984m	9.008ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.783m	5.831ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.278m	4.933ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.728m	2.337ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.462m	3.082ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.654m	2.533ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.549m	2.671ms	1	1	100.00
		chip_sw_uart_smoketest	2.801m	3.535ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.899m	3.266ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.453m	4.442ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.220h	60.259ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.076m	15.018ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.893m	6.701ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.247m	3.397ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.223m	3.930ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.930h	53.696ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.016h	55.587ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.079m	2.594ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.079m	2.594ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.087h	28.558ms	1	1	100.00
		chip_same_csr_outstanding	26.329m	15.521ms	1	1	100.00
		chip_csr_hw_reset	2.089m	4.294ms	1	1	100.00
		chip_csr_rw	3.437m	3.625ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.087h	28.558ms	1	1	100.00
		chip_same_csr_outstanding	26.329m	15.521ms	1	1	100.00
		chip_csr_hw_reset	2.089m	4.294ms	1	1	100.00
		chip_csr_rw	3.437m	3.625ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.700s	773.562us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.340s	44.381us	1	1	100.00
		xbar_smoke_large_delays	47.240s	7.013ms	1	1	100.00
		xbar_smoke_slow_rsp	1.061m	6.631ms	1	1	100.00
		xbar_random_zero_delays	22.600s	380.545us	1	1	100.00
		xbar_random_large_delays	4.244m	44.493ms	1	1	100.00
		xbar_random_slow_rsp	43.000s	4.942ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	34.110s	1.295ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.900s	961.045us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	29.980s	1.435ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.900s	961.045us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	46.940s	865.422us	1	1	100.00
		xbar_access_same_device_slow_rsp	6.244m	43.245ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	16.020s	369.565us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.087m	1.515ms	1	1	100.00
		xbar_stress_all_with_error	3.750s	6.596us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.173m	3.642ms	1	1	100.00
		xbar_stress_all_with_reset_error	28.120s	135.134us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.076m	15.018ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	40.329m	29.157ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	43.251m	15.996ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.658m	10.758ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.778m	17.520ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.360m	16.373ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	44.427m	15.787ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.984m	15.914ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.030s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.610s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.590s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	19.620s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.910s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	19.370s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.210s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.450s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.700s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.120s	10.360us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.390s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.060s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.470s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.410s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.040s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.760s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.750s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.060s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.660s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.290s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.930s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.250s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.750s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.260s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.680s	10.200us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.361m	10.950ms	1	1	100.00
		rom_e2e_asm_init_dev	41.326m	15.442ms	1	1	100.00
		rom_e2e_asm_init_prod	40.836m	16.279ms	1	1	100.00
		rom_e2e_asm_init_prod_end	41.355m	15.789ms	1	1	100.00
		rom_e2e_asm_init_rma	38.932m	15.379ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	40.739m	16.513ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.462m	15.802ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.206m	14.996ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.528m	15.745ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.822m	34.658ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.822m	34.658ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.433m	2.450ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.075m	3.379ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.114m	2.619ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.546m	3.400ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	28.627m	11.891ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.854m	2.461ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.671m	4.858ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.737m	6.089ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.135m	5.266ms	1	1	100.00
		chip_plic_all_irqs_10	4.065m	3.718ms	1	1	100.00
		chip_plic_all_irqs_20	6.954m	4.155ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.679m	3.175ms	0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.995m	11.496ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.983m	4.234ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.203m	2.759ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.917m	7.169ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.416m	7.704ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.678m	8.066ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.351h	255.140ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.933m	4.283ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.783m	5.831ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.933m	4.283ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.376m	7.089ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.376m	7.089ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.859m	7.570ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.852m	5.868ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.343m	5.749ms	1	1	100.00
		chip_sw_aes_idle	2.546m	3.400ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.602m	2.368ms	1	1	100.00
		chip_sw_kmac_idle	1.775m	2.405ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.031m	4.033ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.926m	4.150ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.303m	4.539ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.274m	4.628ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	14.658m	9.531ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.211m	3.616ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.035m	4.720ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.522m	4.216ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.244m	4.183ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.726m	4.489ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.932m	5.160ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.364m	7.670ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.995m	5.414ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.522m	4.216ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.244m	4.183ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.723m	4.392ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.111m	6.138ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.072m	18.844ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.075m	3.379ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.296m	6.742ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.269m	3.045ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	27.223m	13.757ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.823m	2.742ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.155m	4.957ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.990m	2.987ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.212m	2.914ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.195m	4.649ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.808m	7.301ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.759m	24.304ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.388m	2.339ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.427m	2.888ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	11.526m	7.986ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.652m	2.842ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.709m	4.940ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.619m	21.175ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	29.988m	15.689ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.364m	7.670ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.898m	4.590ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.752m	4.041ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.737m	6.089ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.917m	7.169ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.064m	6.814ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.593m	3.359ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.654m	5.501ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.117m	2.815ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.139h	25.997ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.354m	3.279ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.064m	6.665ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.354m	3.279ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.064m	6.814ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.878m	2.929ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.789m	16.537ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.117m	5.811ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.111m	6.138ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.603m	4.257ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.723m	4.392ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.036h	42.635ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.789m	16.537ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.277m	3.826ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	25.623m	12.105ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.454m	5.744ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.036h	42.635ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.454m	5.744ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.454m	5.744ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.454m	5.744ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.454m	5.744ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.737m	6.089ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.619m	11.754ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.992m	4.924ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.963m	5.197ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.963m	5.197ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.544m	2.616ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.269m	3.045ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.602m	2.368ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.495m	3.134ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.654m	3.863ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.902m	5.411ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.584m	4.825ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.505m	5.037ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.286m	3.606ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	25.623m	12.105ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	27.223m	13.757ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	24.795m	12.114ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	28.627m	11.891ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.591m	13.042ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.090m	2.443ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.721m	2.920ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.823m	2.742ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	25.623m	12.105ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.519m	2.894ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	15.524m	7.619ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.775m	2.405ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.671m	4.858ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	6.291m	6.760ms	1	1	100.00
		chip_tap_straps_rma	1.394m	2.531ms	1	1	100.00
		chip_tap_straps_prod	1.787m	3.028ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.140m	3.411ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	23.074m	10.742ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.454m	5.744ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.036h	42.635ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.257m	2.909ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.500m	5.329ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.566m	6.555ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.010m	5.965ms	0	1	0.00
		chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.623m	12.105ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.138m	9.027ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.119m	8.951ms	1	1	100.00
		chip_prim_tl_access	4.619m	11.754ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.995m	5.414ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.211m	3.616ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.035m	4.720ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.522m	4.216ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.244m	4.183ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.726m	4.489ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.932m	5.160ms	1	1	100.00
		chip_tap_straps_dev	6.291m	6.760ms	1	1	100.00
		chip_tap_straps_rma	1.394m	2.531ms	1	1	100.00
		chip_tap_straps_prod	1.787m	3.028ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.731m	8.078ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.875m	3.793ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.665m	3.397ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.595m	2.903ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.640m	3.511ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	26.897m	26.190ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.731m	8.078ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.161h	50.523ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.124h	49.756ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.318m	10.498ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.125h	49.220ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	26.897m	26.190ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.320m	2.769ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.125m	2.430ms	1	1	100.00
		rom_volatile_raw_unlock	1.298m	2.173ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.688m	16.906ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.072m	18.844ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.343m	5.749ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.343m	5.749ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.343m	5.749ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.531m	3.312ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.789m	16.537ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.531m	3.312ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.623m	12.105ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.298m	4.503ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.623m	2.401ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.789m	16.537ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.531m	3.312ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.623m	12.105ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.298m	4.503ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.623m	2.401ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.846m	3.800ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.140m	3.411ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.257m	2.909ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.500m	5.329ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.566m	6.555ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.010m	5.965ms	0	1	0.00
		chip_sw_lc_ctrl_transition	10.503m	11.259ms	1	1	100.00
		chip_prim_tl_access	4.619m	11.754ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.619m	11.754ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.472m	8.466ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.032m	7.520ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.618m	24.683ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.776m	7.502ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.764m	6.752ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.652m	5.788ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.536m	20.681ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	3.709m	5.992ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	5.376m	7.089ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.316m	11.810ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.516m	5.336ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.032m	7.520ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.256m	4.437ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	35.368m	30.601ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.560m	7.445ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.478m	6.197ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.463m	22.577ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.872m	6.857ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.387m	9.784ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	29.998m	31.501ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.159m	3.315ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.737m	6.089ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.138m	9.027ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.138m	9.027ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.387m	9.784ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.463m	22.577ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.516m	5.336ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.783m	5.831ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.273m	4.025ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.994m	3.673ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.197m	4.748ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.995m	11.496ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.364m	2.961ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.737m	6.089ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.416m	7.704ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.417m	4.608ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.335m	4.492ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.115m	2.968ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.623m	2.401ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.994m	3.673ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.994m	3.673ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.383m	10.373ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.777m	13.400ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.273m	4.025ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.481m	4.828ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.280m	5.538ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.394m	2.531ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	2.731m	8.078ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.135m	5.266ms	1	1	100.00
		chip_plic_all_irqs_10	4.065m	3.718ms	1	1	100.00
		chip_plic_all_irqs_20	6.954m	4.155ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.816m	3.025ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.811m	3.452ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.076m	15.018ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.272m	6.563ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.955m	3.582ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.188m	3.568ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.269m	2.999ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.298m	4.503ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.155m	4.957ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.632m	8.325ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.753m	6.988ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.119m	8.951ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.737m	6.089ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.478m	6.089ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.872m	6.857ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.003m	23.575ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.134m	2.938ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.170m	3.324ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.956m	4.405ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.003m	23.575ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.003m	23.575ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.856m	11.612ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.856m	11.612ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.048m	6.162ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.822m	34.658ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.943m	2.756ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.718m	2.411ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.597m	3.246ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.570m	4.139ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.931m	8.152ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.450h	31.424ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	32.199m	12.103ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.842m	3.307ms	1	1	100.00
V2		TOTAL			227	275	82.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.908m	2.664ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.825m	2.246ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.694h	72.000ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.139m	6.317ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	20.052m	12.408ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.427m	12.283ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.380m	13.305ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.492m	5.093ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.298m	4.922ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.492m	5.169ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.963s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.081m	4.632ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.740m	2.561ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	7.948m	4.051ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.682m	7.448ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.445m	2.106ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.967m	4.487ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.209m	2.382ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.541m	2.469ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.188m	4.652ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.841m	4.345ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.387m	9.784ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	20.052m	12.408ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.427m	12.283ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.380m	13.305ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.057m	5.811ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.737m	6.089ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.550h	38.190ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.550h	38.190ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.627m	3.522ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.691m	4.138ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.722m	18.273ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.494m	3.372ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.732m	5.280ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	34.184m	28.944ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.974m	3.221ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.410m	2.621ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.739m	3.565ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.625s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.014m	3.013ms	1	1	100.00
		TOTAL			271	326	83.13

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.28354474125607163023376408820581802611441312809449336058210952072861079855522
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.53545164213359068004059359621341527575039199400480981683140131969479011238480
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.9101530900154880201765794678417472695083017494381510746919206719770126788192
    Line 526, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.28848011562873235144954425435646389053914732491837693264002034924120598025492
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.61557504387416967382899778707577673670462582104966077826089035039172568464322
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.29397111267615096643579739635765298951156976329895186968006825389727872472992
    Line 475, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.77334619936615610691602729702605236404337351085840716495964415082807501098247
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.57896170365227525211302227909402690288480749685558057328085840907201128260492
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.31640854665367162468681087794339132787487599861574103065364048913401692173566
    Line 481, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.106761317075348153350283317252129152502628569836224245836071705815111405539000
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.29032106617573471382763987739144154426673058104616021993715438757443255048362
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 5991.950000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5991.950000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.44324831089541181709334175366826779833131169181234618832230338605629233699495
    Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6752.440000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6752.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.52081120125009628900013558025419211623009821760871321052423246719711360061415
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7089.468500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7089.468500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.100420308057900575629717335035282948729886186592752596274274644062412266362238
    Line 571, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.32446030356920288046967091051801012699570478815579925703626850832992051510801
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.64342658544437548197458544743211955750407842718943401353321343658407594470072
    Line 518, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.101225505775540516278959079077052777638388583194467883168046921633272486059949
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2469.140752 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2469.140752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.54266375073664733455787598081192731549986846951386750732873171958817022599593
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3359.309144 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3359.309144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:

Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.

0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.92330363851484305174866381407888155716070731083767832553884891874890120485341
Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 7939579696ps failed at 7939579696ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 7939663024ps failed at 7939663024ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

Test rom_e2e_shutdown_output has 1 failures.

0.rom_e2e_shutdown_output.46512082630923399510173501610467151616283134329959696961611102719965736538037
Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 20037224157ps failed at 20037224157ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 20037404045ps failed at 20037404045ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.53937731128280604909944530551784665852865061393408156463432148148830224876551
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.164s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.14367623949407257487930825864363085427941187691315509542945900649220963360893
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.169s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.96233741081284313243196681563547997834854980391271700041293303713157342193661
    Line 556, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.90483365534975374091500909588549114547467367899707601369899380863881143998976
    Line 524, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.10866553114343646950055597350812157198980960681826943604297287344797711988936
    Line 559, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.50030014008594370803933778391851952958584190360629703954448860825515681829067
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.85853782558744896061307750734861597773494213251227039731331783961279929142064
    Line 570, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2255.732000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2255.732000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.37096838945825873778847582681970262388503433390835571797346853465355593114600
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3582.007666 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3582.007666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.55310209154344130186218269593055971556197907908136453475722380562740550057654
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 5964.973840 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 5964.973840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.43305170500961043034939161202194215678434602710931538018286435317681872958404
    Line 436, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 28943.960185 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 28943.960185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79998) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.11871008469459935112385907489039216885315609337151833653456497397003647986870
Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3672.926880 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79998) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3672.926880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.42012253116974299673421738875664596797172357495409239661899628751700509109370
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11612.389854 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11612.389854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.24195613524093336939966804897684061175354462575946863587125773150690749995924
    Line 421, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34657.986272 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34657.986272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.47761322919333591854620217873797370388321923568004704621585978425352953370108
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2461.140597 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2461.140597 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.105095650596853866523463836919385508826299183808268663679460828861737670531492
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2758.867844 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2758.867844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.51810704822441670859753086589868515695000121484606489255478197302670268541286
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_alert_handler_entropy has 1 failures.
  - 0.chip_sw_alert_handler_entropy.83271724271694248128952107864167556618090276974292068684584795152305779725644
    Line 522, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log
```
  UVM_ERROR @ 3174.834528 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 3174.834528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.62095128265395819112562758314100919619179879553440999281072068462769311789200
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3133.735630 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3133.735630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(reset_cause == HwReq)' has 1 failures:
- Test chip_sw_sensor_ctrl_alert has 1 failures.
  - 0.chip_sw_sensor_ctrl_alert.103335051092521439212257868284269008677379381562343757458845633116744643218436
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 2688.077316 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 2688.077316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32704) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.65488980619193168877858184399619284307226256418339735327238732077841147250446
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2593.907760 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32704) { a_addr: 'h10494  a_data: 'h88c3c5ac  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h18d20  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2593.907760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.93151405750385667362381628321058317432062707958114144850724004716280724380356
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3565.258100 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3565.258100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.80091044978480040095791817956609647959353007674362210926064165166433497644383
    Line 242, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 8078.345275 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1064c read out mismatch
  UVM_INFO @ 8078.345275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.61780374173992707303281996923187982429785900735946510900989257287866633749233
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2245.551897 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2245.551897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.111428751284993033103163373664969252165774749723958932036963534386320515387940
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3397.287000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3397.287000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.92438221998885229851137351625315950756987687321760101961299781272515896150636
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3930.039500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3930.039500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.4902251566276062625820157030984101782656966794855920798349430936143034431631
    Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 15882.867409 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 15882.867409 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.60618910614289365064918946372109777003318697600958049603549892382716455645682
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.7089750798220751342788506650362586687406240156016734987575085991043457507550
    Line 539, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216190) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.30728133803237773278268936091648133773440604930100947767071456125923349806270
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 4979.877328 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216190) { a_addr: 'h10734  a_data: 'hb7b3422c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a97a  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4979.877328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---