ADC_CTRL Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.050s	6.171ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	0.980s	770.902us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.980s	335.486us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	14.970s	26.622ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.540s	1.131ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.400s	412.144us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.980s	335.486us	1	1	100.00
		adc_ctrl_csr_aliasing	2.540s	1.131ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.646m	161.436ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	14.216m	489.762ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.547m	332.211ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	6.483m	485.359ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1.133m	181.952ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.162m	195.181ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.288m	487.610ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.334m	177.833ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	1.160s	5.478ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.249m	43.330ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	40.370s	107.517ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	15.897m	657.819ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.530s	304.312us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.140s	428.768us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.340s	643.628us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.340s	643.628us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	0.980s	770.902us	1	1	100.00
		adc_ctrl_csr_rw	0.980s	335.486us	1	1	100.00
		adc_ctrl_csr_aliasing	2.540s	1.131ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.310s	4.639ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	0.980s	770.902us	1	1	100.00
		adc_ctrl_csr_rw	0.980s	335.486us	1	1	100.00
		adc_ctrl_csr_aliasing	2.540s	1.131ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.310s	4.639ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	14.130s	7.551ms	1	1	100.00
		adc_ctrl_tl_intg_err	7.750s	4.254ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.750s	4.254ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.190s	10.821ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00