EDN Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.030s	54.736us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.800s	70.292us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.760s	18.301us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.220s	1.085ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.820s	50.510us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.040s	34.261us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.760s	18.301us	1	1	100.00
		edn_csr_aliasing	0.820s	50.510us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.430s	50.188us	1	1	100.00
V2	csrng_commands	edn_genbits	1.430s	50.188us	1	1	100.00
V2	genbits	edn_genbits	1.430s	50.188us	1	1	100.00
V2	interrupts	edn_intr	1.060s	26.642us	1	1	100.00
V2	alerts	edn_alert	0.980s	61.376us	1	1	100.00
V2	errs	edn_err	1.020s	70.629us	1	1	100.00
V2	disable	edn_disable	0.920s	12.822us	1	1	100.00
		edn_disable_auto_req_mode	1.020s	39.351us	1	1	100.00
V2	stress_all	edn_stress_all	2.410s	976.624us	1	1	100.00
V2	intr_test	edn_intr_test	1.110s	14.358us	1	1	100.00
V2	alert_test	edn_alert_test	0.910s	70.023us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.910s	143.484us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.910s	143.484us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.800s	70.292us	1	1	100.00
		edn_csr_rw	0.760s	18.301us	1	1	100.00
		edn_csr_aliasing	0.820s	50.510us	1	1	100.00
		edn_same_csr_outstanding	1.100s	19.826us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.800s	70.292us	1	1	100.00
		edn_csr_rw	0.760s	18.301us	1	1	100.00
		edn_csr_aliasing	0.820s	50.510us	1	1	100.00
		edn_same_csr_outstanding	1.100s	19.826us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.870s	1.217ms	1	1	100.00
		edn_tl_intg_err	1.350s	96.711us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.970s	26.902us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.980s	61.376us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.870s	1.217ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.870s	1.217ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.870s	1.217ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.870s	1.217ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.980s	61.376us	1	1	100.00
		edn_sec_cm	6.870s	1.217ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.980s	61.376us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.350s	96.711us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.367m	4.552ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00