HMAC Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.730s 640.089us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.660s 21.965us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.900s 376.257us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.910s 3.256ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.140s 3.513ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.200s 21.637us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.900s 376.257us 1 1 100.00
hmac_csr_aliasing 6.140s 3.513ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 7.560s 2.318ms 1 1 100.00
V2 back_pressure hmac_back_pressure 37.260s 3.337ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.304m 28.076ms 1 1 100.00
hmac_test_sha384_vectors 5.851m 10.341ms 1 1 100.00
hmac_test_sha512_vectors 6.231m 11.177ms 1 1 100.00
hmac_test_hmac256_vectors 7.840s 434.762us 1 1 100.00
hmac_test_hmac384_vectors 9.320s 1.321ms 1 1 100.00
hmac_test_hmac512_vectors 8.480s 515.701us 1 1 100.00
V2 burst_wr hmac_burst_wr 3.410s 1.440ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.136m 2.225ms 1 1 100.00
V2 error hmac_error 1.209m 15.418ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 55.670s 17.816ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.730s 640.089us 1 1 100.00
hmac_long_msg 7.560s 2.318ms 1 1 100.00
hmac_back_pressure 37.260s 3.337ms 1 1 100.00
hmac_datapath_stress 4.136m 2.225ms 1 1 100.00
hmac_burst_wr 3.410s 1.440ms 1 1 100.00
hmac_stress_all 1.322m 10.382ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.730s 640.089us 1 1 100.00
hmac_long_msg 7.560s 2.318ms 1 1 100.00
hmac_back_pressure 37.260s 3.337ms 1 1 100.00
hmac_datapath_stress 4.136m 2.225ms 1 1 100.00
hmac_wipe_secret 55.670s 17.816ms 1 1 100.00
hmac_test_sha256_vectors 3.304m 28.076ms 1 1 100.00
hmac_test_sha384_vectors 5.851m 10.341ms 1 1 100.00
hmac_test_sha512_vectors 6.231m 11.177ms 1 1 100.00
hmac_test_hmac256_vectors 7.840s 434.762us 1 1 100.00
hmac_test_hmac384_vectors 9.320s 1.321ms 1 1 100.00
hmac_test_hmac512_vectors 8.480s 515.701us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.730s 640.089us 1 1 100.00
hmac_long_msg 7.560s 2.318ms 1 1 100.00
hmac_back_pressure 37.260s 3.337ms 1 1 100.00
hmac_datapath_stress 4.136m 2.225ms 1 1 100.00
hmac_burst_wr 3.410s 1.440ms 1 1 100.00
hmac_error 1.209m 15.418ms 1 1 100.00
hmac_wipe_secret 55.670s 17.816ms 1 1 100.00
hmac_test_sha256_vectors 3.304m 28.076ms 1 1 100.00
hmac_test_sha384_vectors 5.851m 10.341ms 1 1 100.00
hmac_test_sha512_vectors 6.231m 11.177ms 1 1 100.00
hmac_test_hmac256_vectors 7.840s 434.762us 1 1 100.00
hmac_test_hmac384_vectors 9.320s 1.321ms 1 1 100.00
hmac_test_hmac512_vectors 8.480s 515.701us 1 1 100.00
hmac_stress_all 1.322m 10.382ms 1 1 100.00
V2 stress_all hmac_stress_all 1.322m 10.382ms 1 1 100.00
V2 alert_test hmac_alert_test 0.580s 14.889us 1 1 100.00
V2 intr_test hmac_intr_test 0.690s 35.431us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.700s 1.055ms 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.700s 1.055ms 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.660s 21.965us 1 1 100.00
hmac_csr_rw 0.900s 376.257us 1 1 100.00
hmac_csr_aliasing 6.140s 3.513ms 1 1 100.00
hmac_same_csr_outstanding 1.760s 1.056ms 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.660s 21.965us 1 1 100.00
hmac_csr_rw 0.900s 376.257us 1 1 100.00
hmac_csr_aliasing 6.140s 3.513ms 1 1 100.00
hmac_same_csr_outstanding 1.760s 1.056ms 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.740s 41.073us 1 1 100.00
hmac_tl_intg_err 3.170s 236.922us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.170s 236.922us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.730s 640.089us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.610s 118.969us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.256m 1.774ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.730s 14.541us 1 1 100.00
TOTAL 28 28 100.00