I2C Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.930s	5.958ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.860s	1.231ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.820s	50.650us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.850s	79.473us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.200s	278.523us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.120s	233.514us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.240s	129.187us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.850s	79.473us	1	1	100.00
		i2c_csr_aliasing	1.120s	233.514us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.260s	64.673us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.948m	7.146ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	32.540s	18.697ms	1	1	100.00
V2	host_override	i2c_host_override	0.860s	54.845us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.031m	4.869ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.210m	1.797ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.840s	60.154us	1	1	100.00
		i2c_host_fifo_fmt_empty	11.650s	354.137us	1	1	100.00
		i2c_host_fifo_reset_rx	4.970s	243.256us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	52.800s	2.675ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	20.260s	3.464ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.860s	165.399us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.470s	3.454ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	10.150m	37.251ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.810s	3.855ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	25.640s	778.704us	1	1	100.00
		i2c_target_intr_smoke	4.460s	1.008ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.410s	256.130us	1	1	100.00
		i2c_target_fifo_reset_tx	1.110s	208.763us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	28.190s	26.408ms	1	1	100.00
		i2c_target_stress_rd	25.640s	778.704us	1	1	100.00
		i2c_target_intr_stress_wr	52.630s	18.075ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.300s	2.416ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.020s	1.995ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.210s	3.819ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.750s	10.694ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.710s	498.600us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.910s	86.908us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	32.540s	18.697ms	1	1	100.00
		i2c_host_perf_precise	2.290s	385.230us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	20.260s	3.464ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	13.940s	1.466ms	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.180s	2.379ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.000s	1.640ms	1	1	100.00
		i2c_target_nack_txstretch	1.440s	276.575us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.120s	238.793us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.440s	517.737us	1	1	100.00
V2	alert_test	i2c_alert_test	0.750s	23.066us	1	1	100.00
V2	intr_test	i2c_intr_test	0.880s	24.747us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.790s	452.430us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.790s	452.430us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.820s	50.650us	1	1	100.00
		i2c_csr_rw	0.850s	79.473us	1	1	100.00
		i2c_csr_aliasing	1.120s	233.514us	1	1	100.00
		i2c_same_csr_outstanding	1.170s	119.214us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.820s	50.650us	1	1	100.00
		i2c_csr_rw	0.850s	79.473us	1	1	100.00
		i2c_csr_aliasing	1.120s	233.514us	1	1	100.00
		i2c_same_csr_outstanding	1.170s	119.214us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.240s	136.473us	1	1	100.00
		i2c_sec_cm	0.860s	155.351us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.240s	136.473us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.160s	1.373ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.260s	562.792us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.790s	1.578ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.88481055328980816795254273158392937891817396897336589688886887966693941453630
      Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1372917128 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1372917128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.114713374596858368970777717257532376040821724271806290804686290297303408230405
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1578171675 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1578171675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.63616365099342398240700856543644104466410852907654666087161600191823462344844
      Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  64672727 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  64672727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.443028413360249275574118427359281522040444858436341157822873874444485932780
      Line 151, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 7146242555 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @2435437
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.21952111815443859505681571017857529339853784440798829669352361591794077877649
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 3454104423 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 3454104423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.109794225805623210802835162260117198755414737038373979309731625100434595628131
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 562792413 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 562792413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.106652487892319895600753057839720177783730435275509764634671676042584044064695
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10693791774 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10693791774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.72169305509832517387567342786848054353134727580979044339902903053254956406829
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 165398677 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------