| V1 |
smoke |
kmac_smoke |
57.390s |
13.213ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.130s |
93.185us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.130s |
142.887us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
10.420s |
303.125us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.220s |
150.989us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.390s |
201.459us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.130s |
142.887us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.220s |
150.989us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.790s |
39.609us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.280s |
31.086us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
16.073m |
23.286ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
17.529m |
27.875ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
35.116m |
366.696ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
31.035m |
154.447ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
22.503m |
90.384ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
12.947m |
9.386ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.231m |
8.964ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
34.358m |
534.368ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
3.130s |
85.110us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.700s |
85.752us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
1.840m |
22.407ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.828m |
5.860ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
2.862m |
5.660ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
3.961m |
44.072ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
4.510m |
53.343ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
4.200s |
352.253us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
5.920s |
398.744us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
0.840s |
11.677us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.450s |
41.628us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
31.610s |
4.188ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
4.210s |
810.184us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
15.648m |
13.648ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.890s |
124.482us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.040s |
21.184us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.820s |
288.896us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.820s |
288.896us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.130s |
93.185us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.130s |
142.887us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.220s |
150.989us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.260s |
62.168us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.130s |
93.185us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.130s |
142.887us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.220s |
150.989us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.260s |
62.168us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.610s |
897.290us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.610s |
897.290us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.610s |
897.290us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.610s |
897.290us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.140s |
282.245us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
41.910s |
5.652ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
1.900s |
60.380us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
1.900s |
60.380us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
4.210s |
810.184us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
57.390s |
13.213ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
1.840m |
22.407ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.610s |
897.290us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
41.910s |
5.652ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
41.910s |
5.652ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
41.910s |
5.652ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
57.390s |
13.213ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
4.210s |
810.184us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
41.910s |
5.652ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
2.802m |
15.514ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
57.390s |
13.213ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
2.192m |
106.009ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |